The following publications are possibly variants of this publication:
- A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOSBing Lyu, Yun Yin, Xiaobao Yu, Baoyong Chi. asicon 2015: 1-4 [doi]
- A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOSXiaoRan Wang, Tianwei Liu, Shita Guo, Mitchell A. Thornton, Ping Gui. tvlsi, 28(1):12-22, 2020. [doi]
- Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA ToolsRicardo Martins 0003, Nuno Lourenço 0003, Nuno Horta, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins. tcas, 67-I(11):3965-3977, 2020. [doi]