An implementation of hardware accelerator using dynamically reconfigurable architecture - researchr publication authors

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Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano. An implementation of hardware accelerator using dynamically reconfigurable architecture. In 2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006. pages 1-38, IEEE, 2006. [doi]

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