Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano. An implementation of hardware accelerator using dynamically reconfigurable architecture. In 2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006. pages 1-38, IEEE, 2006. [doi]
@inproceedings{YoshikawaYA06,
title = {An implementation of hardware accelerator using dynamically reconfigurable architecture},
author = {Takashi Yoshikawa and Yutaka Yamada and Shigehiro Asano},
year = {2006},
doi = {10.1109/HOTCHIPS.2006.7477752},
url = {http://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2006.7477752},
researchr = {https://researchr.org/publication/YoshikawaYA06},
cites = {0},
citedby = {0},
pages = {1-38},
booktitle = {2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006},
publisher = {IEEE},
isbn = {978-1-4673-8867-2},
}