A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS - researchr publication authors

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Kunzhi Yu, Xuqiang Zheng, Ke Huang, Ma Xuan, Ziqiang Wang, Chun Zhang, Zhihua Wang. A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. pages 1-4, IEEE, 2013. [doi]

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