Kunzhi Yu, Xuqiang Zheng, Ke Huang, Ma Xuan, Ziqiang Wang, Chun Zhang, Zhihua Wang. A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013. pages 1-4, IEEE, 2013. [doi]
@inproceedings{YuZHXWZW13,
title = {A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS},
author = {Kunzhi Yu and Xuqiang Zheng and Ke Huang and Ma Xuan and Ziqiang Wang and Chun Zhang and Zhihua Wang},
year = {2013},
doi = {10.1109/VLDI-DAT.2013.6533835},
url = {http://dx.doi.org/10.1109/VLDI-DAT.2013.6533835},
researchr = {https://researchr.org/publication/YuZHXWZW13},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4435-7},
}