The following publications are possibly variants of this publication:
- A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOSKunzhi Yu, Ziqiang Wang, Xuan Ma, Xuqiang Zheng, Chun Zhang, Zhihua Wang. mwscas 2012: 936-939 [doi]
- A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOSShijie Hu, Chen Jia, Ke Huang, Chun Zhang, Xuqiang Zheng, Zhihua Wang. iscas 2012: 309-312 [doi]
- A 40 Gb/s PAM4 SerDes Receiver in 65nm CMOS TechnologyWeifeng Fu, Qingsheng Hu, Rong Wang. ccece 2018: 1-4 [doi]
- A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOSKe Huang, Ziqiang Wang, Xuqiang Zheng, Xuan Ma, Kunzhi Yu, Chun Zhang, Zhihua Wang. mwscas 2012: 932-935 [doi]
- A 21-Gb/s, 0.96-pJ/bit serial receiver with non-50% duty-cycle clocking 1-tap decision feedback equalizer in 65nm CMOSYang You, Sudipto Chakraborty, Rui Wang, Jinghong Chen. asscc 2015: 1-4 [doi]