Table of Contents

• ReNoC-ML: Reliability-Aware Network-on-Chip Performance Modeling Using Machine LearningZhuofan Lin, Yang Wei Lim, Yongfu Li 0002, Fakhrul Zaman Rokhani. 1-5 [doi]
• An Analog-Front-End with Ultra Low-Power in Optical Sensor for FMCW LiDAR SystemYehyeon An, Jonghyun Kim, Seungju Lee, Jinwook Burm. 1-5 [doi]
• A Fully-Integrated LDO with High PSR and Fast Transient Response Using Adaptive Feed-Forward Ripple Cancellation TechniquePengcheng Wang, Renjie Fu, Yunqi Yang, Yilin Xu, Fanxun Cai, Wenjie Deng, Shixuan Wang, Wu Wen, Chong Duan, Hui Zhang. 1-5 [doi]
• Hardware-Efficient VLSI Architecture for L-BFGS Detection in MIMO-OFDM SystemsXuenan Wang, Yijing Yang, Chenggang Yan, Bi-Wu, Ke Chen. 1-5 [doi]
• A 55 Mhz -Bandwidth Sub-μV-Offset High-Precision Amplifier with Two-Step Automatic Offset CalibrationYang Zhang, Zi Wang, Mingyi Chen. 1-5 [doi]
• CIPHERX: A Unified High-Efficiency AES Encryption and CMAC Authentication Accelerator for Edge ApplicationsSreyas Janamanchi, G. Pradyumna, Chinmay Krishna R, Madhav Rao. 1-5 [doi]
• FCP-LLM: Functional Coverpoint Plan Generation Using LLM in Early Design Verification StageZhuofan Lin, Zixian Guo, Chao Wang 0101, Ruixin Zheng, Yuxin Ji, Yang Wei Lim, Yuhang Zhang 0008, Fakhrul Zaman Rokhani, Yongfu Li 0002. 1-5 [doi]
• Design Automation and Optimization of Frequency DividersPoornishwar M, Inban S, S. Ramprasath, Sankaran Aniruddhan. 1-5 [doi]
• Efficient Hardware Architecture for SHA3 Hash Function Implementation in CRYSTALS-Kyber EncryptionTz-Jen Lin, Chang-Jun Lin, Hsiu-Wei Chen, Shih-Hsu Huang, Po-Yuan Chen. 1-5 [doi]
• Lightweight Distil-Whisper and Hardware-Efficient FPGA Acceleration for Edge ASRYijing Yang, Xuenan Wang, Bi-Wu, Chenggang Yan, Ke Chen. 1-5 [doi]
• Advanced Voltage Measurement Unit With On-Chip High-Pass Filters for Battery EIS SystemByeongho Hwang, Yunchae Lee, Jihan Shin, Jinho Park, Uikyoung Lee, Kyeongha Kwon. 1-5 [doi]
• An SSF-Based Fast-Transient LDO as Reference Buffer for a 12-Bit 50-MS/s SAR ADC in 40-nm CMOSPeijuan Ju, Dixian Zhao, Qisong Wu. 1-5 [doi]
• A Quantitative Evaluation Method of Neural Rendering AcceleratorsHayun Oh, Youngjoo Lee. 1-4 [doi]
• AxAdderNet: Combining Approximate Computing to Quantized AdderNetDaeRyong Shin, Min Kee Chang, Hyunjin Kim, Alberto A. Del Barrio. 1-5 [doi]
• Sparsity and Autocorrelation Peak Difference Based Joint Noise Level and Blur Extent EstimationYu-Chieh Yu, Kuan-Lin Chen, Jian-Jiun Ding. 1-5 [doi]
• A Signed-Transfer SRAM Computing-in-Memory Macro with In-Column Reconfiguration Dac and 2Bit/Cycle QuantizationYing Pan, Xin Li 0099, Yuanyang Wang, Jiaqi Chen, Yang Lou, Yifan Wu, Jianxing Zhou, Qiushi Feng, Wenqiang Zhang, Baofa Wu, Chenghu Dai, Yu Liu 0113, Xiulong Wu, Zhiting Lin. 1-5 [doi]
• Experimental Analysis of Quantum Annealing for Satisfiability ProblemsRemma Ukaku, Tomohisa Kawakami, Hiroyuki Tomiyama. 1-4 [doi]
• 3ETSS: An Energy-Efficient Event-Based Tactile Sensing SystemYuncheng Lu, Kiho Seong, Chufeng Yang, Junying Li, Zechen Wang, Si En Timothy Ng, Shibi Varku, Arindam Basu, Nripan Mathews, Tony Tae-Hyoung Kim. 1-5 [doi]
• Dual-Channel Potentiostat for Electrochemical Measurements with ApproximationsKevin Reagen S., Isa Anshori, Infall Syafalni, Nur Ahmadi, Fakhrul Zaman Rokhani, Tutun Juhana, Trio Adiono. 1-5 [doi]
• A Reconfigurable 8-Channel Dual-Mode Neural Stimulator with High-Voltage Compliance and 97% EfficiencyYijun Ye, Yutao Mao, Wenjun Zou, Hui Wu 0010, Xing Liu 0014, Ziqi Tan, Mostafa Katebi, Jie Yang 0033, Mohamad Sawan. 1-4 [doi]
• Accuracy-Enhanced Block Spiking Neural Networks with Convolutional Localized InhibitionChia-Hsuan Mi, Tsu-Ping Lin, Tsu-Chiao Chen, Kun-Chih Jimmy Chen. 1-5 [doi]
• A 5V-to-1V Hybrid Buck Converter with Asynchronized Switched Inductors and Hybrid Controls for Fast Load TransientHaoqiang Deng, Ming Yu, Ruidong Li, Chen Hu, Guoqing Li, Xun Liu 0002, Junmin Jiang. 1-5 [doi]
• A NOR8T SRAM Digital Compute-in-Memory Macro for Sparse and Scalable Edge-AI ProcessingPratham Sharma, Mukul Lokhande, Akash Sankhe, Kwok Tai Chui, Brij Bhooshan Gupta, Santosh Kumar Vishvakarma. 1-5 [doi]
• Efficient MXINT4 Inference via Hardware-Based Dynamic Sparsity Detection and Skip-ActivationYoungchan Kim, Hyun Kim. 1-5 [doi]
• Active Time-Constant Error Compensation in Multi-Bit Continuous-Time Delta-Sigma ModulatorsTobias Wolfer, Eckhard Hennig. 1-5 [doi]
• Improvement of A2C Training Efficiency with FSM-Based Meta-Optimizer on CPU-FPGA PlatformChavakorn Somjaisuk, Yukio Mitsuyama. 1-4 [doi]
• Emulated Peak Current Mode Buck Converter for High Step-Down ApplicationsMinkwang Ji, Jiho Jung, Jihun Oh, Joongho Choi. 1-4 [doi]
• An Ultra-High-Frequency Neural Stimulator Design Compatible for Both 3.3-V and 30-V OutputZiyue Wu, Xu Liu. 1-5 [doi]
• Design Navigation and Exploration of Complementary Ferroelectric FET (CFeFET) for Next-Generation CFET-based Nonvolatile SRAM and Logic-in-Memory ApplicationsYung-Hsuan Huang, Chu-Hsiu Hsu, Yuan-Yu Huang, Pin Su, Po-Tsang Huang. 1-5 [doi]
• APSDCP-Net: Adaptive Patch-Size Dark Channel Prior Network for Single Image DehazingMing-Yang Tu, Kuan-Lin Chen 0001, Jian-Jiun Ding. 1-5 [doi]
• ETA: Efficient Transformer Attention Mapping for ReRAM-Based Compute-In-Memory ArchitecturesJohnny Rhe, Juhong Park, Kang Eun Jeon, Jong Hwan Ko. 1-5 [doi]
• Analog Blocks for 8-Bit SAR ADC: Rail-to-Rail Comparator and Two-Stage Operational Amplifier Designed with Open-Source Tools and Sky130 PDKUriel Jaramillo-Toral, Susana Ortega-Cisneros, Emilio Isaac Baungarten-Leon, Erick Jaramillo-Toral, Héctor Emmanuel Muñoz Zapata. 1-5 [doi]
• On the Data Dependency of the Read Speed of Low-Voltage SRAM with VSS-Assist CircuitryChien-Tung Liu, Yu-Chuan Hou, Tay-Jyi Lin, Jinn-Shyan Wang. 1-5 [doi]
• An Experiment of Neural Prosthesis Based on an Electronic Circuit Spiking Neuron ModelShogo Shirafuji, Hiroyuki Torikai. 1-5 [doi]
• A Configurable RISC-V Vector Processor with FSM-Driven Accelerator for Data-Intensive WorkloadsAkkapolu Sankararao, Vashist Managari, Naveen Kollepara, Binsu J. Kailath. 1-5 [doi]
• A Discontinuously Resonant Operation for Continuously-Scalable-Conversion-Ratio Switched Capacitor Converter with Enhanced Power Efficiency and Output CapabilityHaozhe Zhang, Chuang Wang, Xiaosen Liu, Xuliang Wang, Renwei Chen, Xuchen Men, Feng Wang, Yan Wang 0023. 1-5 [doi]
• Low Fractional Spurs Frequency Synthesizer for Nuclear Magnetic Resonance Measurement SystemsParham Davami, Guillaume Mocquard, Thomas Burger. 1-5 [doi]
• An Enhanced ASAP7 PDK with Power Via Technology for IR Drop and PPA EvaluationMingjie Yu, Jiaqi Dou, Bingyi Ye, Yang Shen, Xiaojin Li, Yanling Shi, Yuhang Zhang, Yabin Sun. 1-5 [doi]
• A 112Gb/s PAM4 Mach-Zehnder modulator Driver in 12nm FinFET with 3.8 V Output Swing for Analog-Digital Co-IntegrationGiovanni Marco Rubino, Alessio De Prà, Danilo Manstretta. 1-5 [doi]
• An 88.6-dB SNDR Discrete-Time Delta-Sigma Modulator Using Two-Stage Floating Inverter Amplifiers in 180-nm CMOSChun-Yang Chiu, Yung-Hui Chung. 1-4 [doi]
• Time-Evolving Bifurcation Phenomena in a Chaotic Circuit with a MemristorTaishi Segawa, Yoko Uwate, Yoshifumi Nishio. 1-4 [doi]
• Energy-Efficient Surveillance via Event-Driven ROI Detection with DVS-CIS FusionMincheol Cha, Keehyuk Lee, Soosung Kim 0003, Hyunsurk Ryu, Xuan Truong Nguyen, Hyuk-Jae Lee. 1-2 [doi]
• An Energy-Efficient Super-Resolution Processor with Enhanced Tiling Artifact ReductionByeungseok Yoo, Sungjin Park, Sunwoo Lee 0005, Dongsuk Jeon. 1-5 [doi]
• A Capacitor-Less LDO with Enhanced Wide Band Power Supply Rejection for Voltage-Controlled OscillatorChengcheng Zhou, Jiawen Yang, Rui Li, Yongsheng Yin, Xu Meng. 1-5 [doi]
• FPGA-Based Real-Time ISP Accelerator Using Low-Cost Line Buffers and Non-Linear FunctionsSeungwoo Hong, Jung Gyu Min, Jin Hyun, Jaehee Kim, Dongyun Kam, Eunji Yoo, Pilsu Kim, Jaehyung Yoo, Hyong-Euk Lee, Youngjoo Lee. 1-5 [doi]
• Alt-FF: A Logic-Level Design of Flip-Flop Control for Side-Channel ProtectionManami Nishimura, Tomoaki Ukezono, Toshinori Sato. 1-5 [doi]
• Hardware-Aware Backpropagation Training for SNNs on Analog, Ultra-Low Power Neuromorphic Hardware Compensating for MismatchMatthias Ochs, Alexander Greif, Max Jamula, Ralf Brederlow. 1-5 [doi]
• Dual-Clock Optimization for Multi-Core Base Conversion in Fully Homomorphic CKKS SchemeRafael Aditya Cahyo W, Handy Jonarta, Muhammad Ogin Hasanuddin, Infall Syafalni, Nana Sutisna, Trio Adiono. 1-4 [doi]
• A 3.35 and 4.18 ppm/°C Dual-Output Bandgap Reference Circuit with Wide Temperature Range Using Curvature and Digital PVT CompensationTzung-Je Lee, Zi-Yi Huang, Aleksandr Vasjanov, Vaidotas Barzdenas. 1-4 [doi]
• A Single-Channel 1-GS/s 62.2-dB Sndr Hybrid Voltage-Time Pipelined ADC with Parallel Conversion Technique in 40-nm CMOSHuilin Zhou, Xinsheng Wang, Congyi Zhang 0004, Chenrui Liang. 1-5 [doi]
• An Ultra-Low Jitter Divider-Less Phase-Locked Loop Using Differential Dual-Edge Sub-Sampling Phase DetectorAnshul Verma, Bishnu Prasad Das. 1-5 [doi]
• A 6T SRAM Analog CIM Macro for 8-Bit MAC with Input/Weight Partitioning for High Signal Margin and ThroughputAbhishek Goel, Cheena Singhal, Dinesh Kushwaha, Sparsh Mittal, Sudeb Dasgupta. 1-5 [doi]
• 2 Resolution FoMShuan Yang, Tai-Hong Chen, Yu-Chi Wang, Chia-Hsi Fang, Chun-Yu Lin, Shan-Chih Tsou, Shon-Hang Wen, Kuan-Dar Chen, Tsung-Hsien Lin. 1-4 [doi]
• RNS Base Conversion Using Optimized Multiword Multipliers for Approximate Modulus SwitchingMuhammad Ogin Hasanuddin, Hanho Lee. 1-5 [doi]
• Comparison of Barrett Modular Reduction with Various Multipliers in the Context of BFV/BGV Homomorphic EncryptionMuhammad Daffa Rasyid, Ardianto Satriawan, Hanho Lee. 1-5 [doi]
• Bit-Preserving Analog Alignment-Based Cross-Domain FP-CIM for LLMsHuiwon Kim, Dongwoo Lew, Jongsun Park. 1-5 [doi]
• A Pipeline-Driven FPGA Accelerator with Memory-Scheduling for Neuromorphic ComputingZhipeng Liao, Tianyang Li, Ziyang Shen, Chaoming Fang, Jie Yang, Mohamad Sawan. 1-5 [doi]
• A 72.7-µW Noise Shaping SAR-Assisted Incremental ADC with Extended Counting Achieving 88.5-dB SNDR and 179.9-dB FoMSNDRYi Huo, Menglian Zhao, Zhichao Tan. 1-5 [doi]
• A Ka-band Low-Noise Amplifier with Co-optimized Magnetic-Coupled Gm-Boosting and Parallel Inductor for 5G FR2 and 6G LEO SATCOMKyoungwoo Kim, Jungro Lee, Jinseok Park, Seungchan Lee. 1-5 [doi]
• A New Narrowband Active Noise Control System with Improved ApplicabilityN. Hara, Y. Xiao, T. Shirakawa, Y. Ma, L. Ma, K. Khorasani. 1-5 [doi]
• RecFlash: Fast Recommendation Inference on NAND Flash-Based In-Storage Computing with Embedding-Optimized Data MappingJangho Baik, Gisan Ji, Wonbo Shim, Sungju Ryu. 1-5 [doi]
• High-Speed Matrix-Thread Co-Optimized NTT Design for ML-KEMGong Chen, Jiansheng Chen, Tianyang Yu, Zhirui Zhang, Bei Wang 0013, Fangyu Zheng, Yijun Cui. 1-5 [doi]
• Uncertainty-Aware Performance Evaluation of Low-Noise Amplers via Generalized Polynomial Chaos Expansion-Based Surrogate ModelHoyeon Shin, Taeyeong Kim, Jiyong Chung, Moon-Kyu Cho, Songnam Hong, Ickhyun Song. 1-5 [doi]
• RoPE on the Fast Track: Latency-Optimized LLM Inference on GPUs with Low-Rank QKV Factorization and Rotary Positional EmbeddingGilhyeon Lee, Jihoon Jang 0001, Kyungmin Goh, Hyun Kim 0001. 1-5 [doi]
• A Wide-Range Standard-Cell-Compatible Voltage Level Shifter with Transition-Controlled Current Generator in 3-nm Nano-Sheet TechnologyAnuj Bhardwaj. 1-4 [doi]
• BWFA-CAT: Bidirectional Wavefront Sequence Alignment with Content-Aware Tiling and its Hardware AcceleratorChia-Hung Lin, Po-Yen Chang, Yi-Chang Lu. 1-5 [doi]
• A 99.1 dB-SNDR CT-DT NS SAR ADC with Two-Stage Stacking Inverter-Cascoded FIAYanzhujun Du, Lingxin Meng, Menglian Zhao, Zhichao Tan. 1-5 [doi]
• Design of Robust Clock-Tree Circuit with Transient-Recovery TechniqueJunhwa Jeong, Jongho Lee, Hoyeon Shin, Ilho Myeong, Ickhyun Song. 1-5 [doi]
• Advanced Techniques for Mitigating Power Supply Induced Jitter in Low-Cost, Multi-Lane, Multi-PHY Timing Controller Solutions in 8 nm FinFETSubhadeep Datta, Ankur Ghosh, Santosh Kumar Reddy, Umamaheswara Reddy Katta, Manohar Seetharam, Byunghyun Lim, Jongjae Ryu, Goeun Kim, Doohee Lim, Sachin Kashyap, Mohit Arora, Bhargavi SPH, Saikat Hazra, Sumanth Chakkirala, Avneesh Singh Verma. 1-4 [doi]
• Mask 3D Parameter Prediction in EUV Lithography by Convolutional Neural NetworkAtsushi Takahashi 0001, Moe Sugiyama, Masayuki Shimoda, Hiroyoshi Tanabe. 1-4 [doi]
• Foscu: Feasibility of Synthetic Mri Generation Via Duo-Diffusion Models for Enhancement of 3D U-Nets in Hepatic SegmentationYoungung Han, Kyeonghun Kim, Seoyoung Ju, Yeonju Jean, Minkyung Cha, Seohyoung Park, Hyeonseok Jung, Nam-Joon Kim, Woo Kyoung Jeong, Ken Ying-Kai Liao, Hyuk-Jae Lee. 1-5 [doi]
• VitalSystem: A FauIt-Tolerant System Architecture for Wafer-Scale IntegrationYiyang Liu, Jinghe Wei, Wenxin Xu, Leran Wang, Huixiang Li, Ying Gao. 1-5 [doi]
• Innovative Strategies for Siamese Network Optimization: Leveraging Multi-Level Mask Guidance in Visual Object TrackingBo-Han Chen, Min-yu Chai, Chai-chi Tsai. 1-5 [doi]
• Periodic Orbits and Hardware Implementation of Permutation XOR Cellular AutomataYosuke Suzuki, Toshimichi Saito. 1-4 [doi]
• A Comparative Study of Adaptive Channel Selection for Resource-Constrained On-Chip Seizure DetectionShanmugam S, Ankur Gupta, Laxmeesha Somappa. 1-5 [doi]
• On the Hardware Efficiency of Short-Length Polarization-Adjusted Convolutional Polar DecodersJunehyuk Oh, Soonhyun Kwon, Dongyun Kam, Youngjoo Lee. 1-5 [doi]
• Memory-Efficient Differential Privacy AcceleratorMuhammad Hamis Haider, Nam-Joon Kim, Hao Zhang 0041, Janier Arias-Garcia, Hyuk-Jae Lee, Seok-Bum Ko. 1-5 [doi]
• A Sub-100 nW Power-on-Reset Circuit with Integrated Brown-Out Detection and Autonomous Power Gating for Edge DevicesInseo Son, Yoochang Kim, Young Ha Hwang. 1-5 [doi]
• A 10-bit 40-MS/s Capacitor-Swapping SAR ADC in 180-nm CMOSYing-Liang Li, Yung-Hui Chung. 1-4 [doi]
• 2D Material Characterisation Using in-Memory Predictive AnalyticsKishan Kartha, Aleena Kabeer, Alex James. 1-5 [doi]
• Design of a Low Phase Noise Quadrature DCO Using Dual Superharmonic Injection in 55nm CMOS for Ka-Band ApplicationsDevesh Bhaskaran, Shashidhar Tantry. 1-5 [doi]
• MPPT Boost Converter with AFE for MIC-Based Solar Power SystemsHaechan Park, Jooyun Oh, Jaehyeok Lee, Sungwan Hong, Joongho Choi. 1-4 [doi]
• Efficient FPGA Implementation of Compressor Trees Based on Generalized Parallel Counter ChainsMugi Noda, Nagisa Ishiura. 1-5 [doi]
• Via-Configurable Routing Network and Hard Macro Adaptability for 28 nm Structured ASICJunyu Lin, Binxu Ning, Jian Yu, Ning Chen, Tianqin Ye, Lei Shen. 1-5 [doi]
• A 63.6-81 GHz Broadband LNA with 22.9 dB Gain and 4.9 dB NF in a 65-nm CMOS TechnologyGuanglai Wu, Yun Fang, Zongming Duan, Yi Zhang 0022, Yufeng Guo, Yongjie Li 0002, Hao Gao 0001. 1-4 [doi]
• A Dual-Mode High Efficient Hardware Architecture Design for Diffusion ModelsTsung-Lin Tsai, Yi-Cheng Lo, Ching-Yao Chen, An-Yeu Andy Wu. 1-5 [doi]
• Performance Evaluation of Adaptive Stochastic Computing Based Image Processing ApproachesKeerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi. 1-4 [doi]
• m Technique for Folded-Cascode OTAs in 22 nm FDSOI TechnologyClaire Mahusay, Cedric Allen Oria, Arcel G. Leynes, Maria Sophia Ralota, Vincent Angelo Bogg's G. Roxas, Marc D. Rosales, Maria Theresa G. de Leon. 1-5 [doi]
• A Derivative-Sign Discrimination Based Calibration Scheme for Timing Skew in Dual-Channel TIADCsXin Li 0099, Mengdi Miao, Ying Pan, Yu Liu 0113, Chenghu Dai, Yongliang Zhou, Xiulong Wu, Zhiting Lin. 1-5 [doi]
• Energy-Efficient ReRAM-Based In-Memory Computing with Dual SNN/ANN ModesChang-Yu Kuo, Tian-Sheuan Chang, Tsung-Heng Tsai. 1-5 [doi]
• An IREE Compiler-Based SoC Design for Efficient on-Device AI Inference AccelerationSuhwan Park, Sangcheol Park, Jin-Ku Kang, Yongwoo Kim. 1-5 [doi]
• FRIEREN: A Lightweight System for Face Resizing Image Detail Quality Evaluation via Robust Estimation of Image NaturalnessYuan Kang Lee, Kuan-Lin Chen, Jian-Jiun Ding. 1-5 [doi]
• A 16 Gb/s 48.9 fJ/b PVT-Tolerant Standard-Cell-Based Receiver for AC-Coupled Chiplet InterconnectsYuki Mitarai, Mototsugu Hamada, Atsutake Kosuge. 1-5 [doi]
• A Study on the Very Small Phase Difference Measurement Circuit Suitable for Integration of Multi-Point Phase Difference Measurement SystemMaa Shimogawa, Takuro Noguchi, Akio Shimizu, Yohei Ishikawa. 1-4 [doi]
• A Sub-Sampling Fast Lock Detector for Fractional-N PLLFanxun Cai, Ziyang Li, Zijie Wang, Yunqi Yang, Pengcheng Wang, Yilin Xu, Lianbo Wu, Hui Zhang. 1-5 [doi]
• An Area-Time Efficient and Generic Accelerator for the Verification of Hash-Based Signature SchemesYueqin Dai, Yifeng Song, Zhongfeng Wang 0001. 1-5 [doi]
• A Simulation-Based Study on Impact of DVS for Side-Channel AttacksRyoma Katsube, Shinichi Nishizawa, Toshinori Sato, Tomoaki Ukezono. 1-5 [doi]
• A Sub-1-V 2-Bit Low-Noise and High-PSRR Low-Dropout Linear Regulator in 65-nm SOI CMOS for 5G ApplicationsLi Dai, Jin Li, Bo Chen, Linqian Zhao, Tao Yuan. 1-5 [doi]
• Fast and Energy-Efficient Pipelined Vedic Multiplier Design for Modern Cryptographic ProcessorsAkkapolu Sankararao, Naveen Kollepara, Vashist Managari, Binsu J. Kailath. 1-5 [doi]
• A High Energy and Area Efficiency DCIM with 2TC Based Dual-Layer Approximate CompressorChing-Yu Chen, Wei-Chih Ho, Chia-Wei Su, I-Chyn Wey. 1-2 [doi]
• A Low-Power PLL with Supply Noise Insensitive VCO in 65nm CMOSThinh Tran-Dinh, Minh Nguyen Quang, Hung Le-Quang, Du Doan-Khanh, Huy Do-Quang, Sang-Gug Lee 0001, Loan Pham-Nguyen. 1-5 [doi]
• A Convolutional Autoencoder-Based System for Point Cloud CompressionLih-Jen Kau, Yong-Wei Liu. 1-5 [doi]
• An Efficient Accelerator for Attention Mechanism Based on Combined-Head Low-Rank Projection and Unified-PE Candidate SelectionXingyuan Hu, Xulong Zhang 0007, Xiao Cong, Haoran Geng, Chongkang Tan, Yuan Du, Li Du. 1-5 [doi]
• An Energy-Efficient Vision Language Model Inference with Importance-aware Token PruningZhamaliddin Kalzhan, Songyeon Hong, Hoi-Jun Yoo. 1-5 [doi]
• A Single-Mode Three-Phase Dual-Path Hybrid Buck-Boost Converter with Extended VCR Range and Always-Reduced Conduction LossXinman Li, Xiongjie Zhang, Yang Jiang 0002, Yan Lu 0002, Rui Paulo Martins, Pui-In Mak. 1-5 [doi]
• A Non-Invasive Ultrasound-Transmission-Based Thermometry Method for Multi-Layer Deep Tissue MonitoringSaebyeok Shin, Jaehong Jung, Mohith Manohara, Anantha P. Chandrakasan, Ahmad Bahai. 1-4 [doi]
• Poincaré Embeddings for Brain Age Estimation and Hierarchical Biomarker DiscoverySeung Woo Heo, Nam Jun Kim, Hyuk-Jae Lee. 1-5 [doi]
• A 151.9-165.9 GHz 8.8% FTR Quadrature Voltage Controlled Oscillator in 28-nm FDSOIWaseem Abbas, Samir Aziri, Christoph Wagner, Golsa Ghiaasi. 1-4 [doi]
• Design Automation for a-IGZO Thin Film Technology Using a Multi-Row Standard Cell ArchitectureYi-Ting Lin, Yalun Tang, Byeonggon Kang, Iris Hui-Ru Jiang, Kenji Nomura, Yuhwa Lo, Lifu Chang, Bill Lin 0001, Chung-Kuan Cheng. 1-5 [doi]
• IR-Aware Weight Remapping Considering Thermal Effect and Stuck-at Faults in RRAM Crossbar ArrayShih-Han Chang, Yi-Lun He, Chien-Nan Jimmy Liu. 1-5 [doi]
• A 10T SRAM-Based PUF Enhanced by In-Memory Computing for Secure AuthenticationNeha Maheshwari, Shivam Vaish, Kwok Tai Chui, Brij Bhooshan Gupta, Santosh Kumar Vishvakarma. 1-5 [doi]
• Flow-Based Compact Droplet Routing Algorithm for MEDA-Based DMFBEmuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi 0001. 1-5 [doi]
• A Hybrid Buck-Boost Converter with Single Duty Cycle Control and Continuous Output CurrentTiantian Tang, Chen Hu, Ming Yu, Xun Liu 0002, Junmin Jiang. 1-5 [doi]
• Novel 4T-2C Ferroelectric Non-Volatile Memory Cell Featuring Non-Destructive ReadNihal Raut, Harshitha Gangu, Vatika Jhanjee, Abhishek Kadam, Veeresh Deshpande. 1-5 [doi]
• ECHO: An Efficient Co-Designed ASR Accelerator with Hardware-Friendly and Audio-Aware AttentionTseng-Jen Li, Tian-Sheuan Chang. 1-5 [doi]
• N-Coupled CMOS Differential Relaxation Oscillators for Deep Oscillatory Neural NetworksKunjeti Dharanidhar Gupta, Srinivasa Chakravarthy, Sankaran Aniruddhan. 1-5 [doi]
• A Simple Control Strategy for Achieving Steady-State Current Balance in a Three-Arm Series Capacitor Step-Down DC-DC ConverterChen-Tung Hsiao, Chung-Yi Li, Chin Hsia, Teo Tee Hui, Chia-Chen Shen. 1-4 [doi]
• THES-SNN: Thresholded Hybrid Encoding with Single-Spike Neurons for Energy-Efficient Spiking Neural NetworksJia Yu, Tianyang Yu, Bi Wu 0002, Ke Chen 0018, Chenggang Yan 0002, Weiqiang Liu 0001. 1-5 [doi]
• A 66.7dB-SNDR Pipelined-SAR ADC with On-Chip Bit-Weight Calibration Achieving ⃤SNDR<2.4dB Across PVT VariationsJinwei Zhang, Haolin Han, Ruili Ren, Shubin Liu 0001, Zhangming Zhu. 1-4 [doi]
• A Low-Power Open-Loop Spread-Spectrum Clock Generator Design for Ref-Clk ApplicationsYuxiao Zhang, Ziwang Cao, Yejuan Zeng, Xu Meng, Yongsheng Yin. 1-5 [doi]
• A 1D Squeezenet-Based Edge Computing System for Arrhythmia Classification in the ElderlyFeng Jiang 0018, Yang Wei Lim, Siti Anom Ahmad, Faisul Arif Ahmad, Luthffi Idzhar Ismail, Ahmed Faeq Hussein, Fakhrul Zaman Rokhani. 1-5 [doi]
• 2/Pixel Simultaneous Energy-Harvesting-and-Sensing 2-by-2 Self-Powered CMOS Image Sensor Pixel Array Using Self-Oscillating Voltage Doubler for Thermal-Aware Zero-Stand-by-Power ImagingKei Awano, Yoshitsune Sugimura, Yuma Ota, You Wu, Keishi Ogura, Hiroaki Kitaike, Kento Okamura, Shufan Xu, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Ruilin Zhang, Hirofumi Shinohara, Kunyang Liu, Kiichi Niitsu. 1-5 [doi]
• 0.3V Specification-Oriented Inverter-Based Otas with NAND-and-NOR CMFB Using Different Standard Cells' StrengthNgo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran, Orazio Aiello. 1-5 [doi]
• Codeword-Aware Data Mapping for Efficient JPEG Decoding on Skyrmion Racetrack MemoryWan-Siang Wu, Yu-Ting Huang, Yu-Rou Shen, Yu-Pei Liang. 1-5 [doi]
• A Sturdy MASH Third-Order Noise-Shaping SAR ADC with Reuse of the SAR ADCJang-hyeon Cho, Sang-Gyu Park. 1-4 [doi]
• A 14-Bit Two Steps 50MS/s SAR-ADC Based on Time-Domain Quantization Utilizing High Linearity VTC MethodBo Song, Yiyao Xiang, Mingsheng Xu. 1-5 [doi]
• A 12-μV Offset Low-Input-Bias-Current High-Precision CMOS Operational Amplifier with Automatic Offset CalibrationKunxun Luo, Jingquan Liu, Mingyi Chen. 1-5 [doi]
• A High-Performance RRAM-Based PMM Accelerator for Lattice-Based PQCYang Chen, Zeren Zhu, Bei Wang 0013, Chenghua Wang, Yijun Cui. 1-5 [doi]
• Leveraging Natural Structured Sparsity for Energy-Efficient Spiking Transformer ProcessingHyunseok Jung, Dongwoo Lew, Jongsun Park 0001. 1-5 [doi]
• A Three-Level Inverting Buck Converter with 5μs Response Time and 20mV Output Ripple for Micro-Led DisplaysGang Liu, Wuxiao Dong, Ruidong Li, Guoqing Li, Junmin Jiang, Xun Liu 0002. 1-5 [doi]
• An L-Band Dual-Low-Noise-Amplifier Bank Ic in 65-nm SOI CMOS with 20-dB Gain for Advanced GNSS Receiver Front EndsLi Dai, Jin Li, Bo Chen, Linqian Zhao, Tao Yuan. 1-5 [doi]
• A 1D Lightweight ShuffleNetV2 for Cardiovascular Disease Detection in a Point-of-Care SystemFeng Jiang 0018, Yang Wei Lim, Siti Anom Ahmad, Faisul Arif Ahmad, Luthffi Idzhar Ismail, Ahmed Faeq Hussein, Fakhrul Zaman Rokhani. 1-5 [doi]
• Highly-Efficient Unified Polynomial Arithmetic Module Architecture for Falcon PQC SchemeQuang Dang Truong, Tuy Tan Nguyen, Hanho Lee. 1-5 [doi]
• A 28nm 20 TOPS/W in-Memory Search Engine with Pre-Charge-Free SRAM-Based TCAM and Hybrid-Match Mechanism for Few-Shot LearningJen-Chieh Wang, Chi-Tse Huang, Chia-Wei Su, Chun-Fu Chen, I-Chyn Wey, Hsiang-Yun Cheng, An-Yeu Wu. 1-5 [doi]
• ML-Pump: A Machine Learning Based Bidirectional Prediction Framework for Charge Pump Design OptimizationAshutosh Singh, Anuj Grover, Abhishek Jain. 1-5 [doi]
• Progressive NAS for Efficient Structural Pruning of Pretrained Language ModelsAmrita Rana, Kyung Ki Kim. 1-4 [doi]
• Nanomechanical Self-Timed Power Management Circuit for Low-Power IoT DevicesGuangwei Liao, Roshan Weerasekera, Dinesh Pamunuwa. 1-5 [doi]
• Comparison of Switched-Capacitor and Low-Q Resonant Switched-Capacitor with High-Density Capacitor in 3-D PackagingDu Zhou, Guigang Cai. 1-5 [doi]
• A Wide Bandwidth TIA with Low Power Consumption for PNN PrototypingL. S. S. Pavan Kumar Chodisetti, Jen-Yu Li, Pradyumna Vellanki, Yung-Jr Hung, Chua-Chin Wang. 1-5 [doi]
• Posit Adder and Multiplier with Variable Input and Output Exponent SizesMin Kee Chang, DaeRyong Shin, Hyunjin Kim, Alberto A. Del Barrio. 1-5 [doi]
• Scalable and High-Performance Number-Theoretic Transform Design for Lattice-Based CryptographyHien Nguyen 0009, Quang Dang Truong, Hanho Lee, Tuy Tan Nguyen. 1-5 [doi]
• Development of Drowsiness Detection in Elderly Drivers Using an AI ChipAsavaron Limsuebchuea, Rakkrit Duangsoithong, Nattha Jindapetch. 1-4 [doi]
• A Dual-Core Mode-Switched L-C Coupled Class-F VCO with 43 % Tuning RangeKastur Roy, Anik Batabyal, Rajesh Zele. 1-5 [doi]
• A 27 GHz Phase-Coupled Distributed Quad-Core Oscillator in 12 nm FinFETValentina Marazzi, Lorenzo Porcheddu, Marco Garampazzi, Enrico Temporiti, Danilo Manstretta. 1-5 [doi]
• A Visualization-Assisted Insect Classification Human-Machine Interface System Based on Spatial Pyramid Pooling CNNSong-Min Ke, Chang-yu Wu, Chang-Yi Chu, Hoh-Siang Liao, Ying-Hsiu Hung, Shin-Chi Lai. 1-5 [doi]
• Cuffless Blood Pressure Estimation Using Wearable Devices Based on Attention Mechanisms and Synthetic Data From Generative ModelsChe-An Chen, Chuan-En Chou, Pei-Yun Tsai 0001, Tzung-Dau Wang. 1-5 [doi]
• Battery-Less and Sensor-Less LoRa Node for Water Turbidity MonitoringArvin Raj Ramesh, Samsuzana Abd Aziz, Norulhuda Mohamed Ramli, Khairudin Nurulhuda, Roberto La Rosa, Orazio Aiello, Fakhrul Zaman Rokhani. 1-5 [doi]
• Implementation and Analysis of Mandarin Lipreading on Edge DevicesYu-Hsuan Tseng, Che-Min Tsai, Chong-Hao Xu, Shanq-Jang Ruan. 1-5 [doi]
• CLCO-S1: Efficient Softmax1 Architecture of Cross Level Collaborative Optimization for TransformerYingqian Chen, Haoran Geng, Cheng Liu, Li Du. 1-5 [doi]
• A V-Band Noise Canceling LNA for Atmospheric Temperature Profiling RadiometersMounika Kare, Anik Batabyal, Rajesh H. Zele. 1-5 [doi]
• Progressive Few-Shot NAS via Multiple Elastic Subsupernets for Efficient Network SearchOscal Tzyh-Chiang Chen, Ya-Yun Cheng, Zih-Rong Lin, Manh-Hung Ha. 1-4 [doi]
• A Memory-Efficient Framework for Deformable Transformer with Neural Architecture SearchWendong Mao, Mingfan Zhao, Jianfeng Guan, Qiwei Dong, Zhongfeng Wang. 1-5 [doi]
• A CMOS SOI 180nm Sub-Ranging Bandgap Reference with 4.5ppm/°C TC Across -40 to 175°CMingrui Wang, Hengchen Zou, Rui Martins, Pui-In Mak, Ka-Meng Lei. 1-5 [doi]
• System-on-Chip Implementation of Deep Learning RF Fingerprinting for Device AuthenticationDuc Dung Vu, Vu Hoang Thang Chau, Ivan Schipper, Mateo Favel, Muhammad Asad Imran Rafique, Bo Li, Ediz Cetin. 1-5 [doi]
• A Perspective on Self-Capacitive Readout Architectures for In-Cell Touch PanelsJun-Seong Kim, Dabin Yun, Sang Weun Kim, Wooseok Jang, Hamin Lee, Seunghoon Ko. 1-2 [doi]
• IoT-Based Elderly Health Management SystemMohd Nazim Mohtar, Siti Anom Ahmad, Fakhrul Zaman Rokhani. 1-3 [doi]
• ChargeFloat-TQ: A Charge-Domain-Based Tracking-Quantized Floating-Point Computing-in-Memory Accelerator MacroYu Liu 0113, Hao Li, Changxin Yue, Xiulong Wu, Chunyu Peng, Wenjuan Lu, Chenghu Dai, Xin Li 0099, Zhiting Lin. 1-5 [doi]
• A 15-20GHz CMOS Variable-Gain Phase Shifter for UAV Detection Radar SystemsHaram Park, Mingyu Lee, Eunchae Jo, Hyeonwon Song, Seungchan Lee, Jinseok Park. 1-3 [doi]
• FPGA Implementation and Analysis on Parallel and Pipeline Approximate Softmax for TransformerAbdullah Celep, Trio Adiono, Infall Syafalni, Nana Sutisna, Nur Ahmadi, Rahmat Mulyawan. 1-5 [doi]
• StripDet: Strip Attention-Based Lightweight 3D Object Detection from Point CloudWeichao Wang, Wendong Mao, Zhongfeng Wang. 1-5 [doi]
• K-Band 65-nm CMOS 2-Stage LNA Using High-Pass Filter for Low-Noise and Neutralization Capacitor for Wideband PerformanceChaeyun Kim, HyoJin Yoon, Jaeyong Lee 0005, Changkun Park. 1-4 [doi]
• Hybrid LDO Having Small-Output Ripple and Fast-Settling at 0.5V Supply Using Dynamic Gate-Voltage Generation and Fast-PD DecisionSeungwan Kim, Younghyun Lim. 1-4 [doi]
• Multi-Channel Quantum-Effect Thin-Film Transistors for Beyond Cmos ApplicationsMohammad Masum Billah, Moath Alathbah, Jung-Bae Kim, Jin Jang. 1-5 [doi]
• Design Considerations for a Third Order Passive Loop Filter in a PLLAsif Rahman, Chithra. 1-5 [doi]
• Layer Sensitivity Mixed-Precision Quantization for Image Super-ResolutionJun-Young Kim, Joo Hyeon Jeon, Sung In Cho. 1-5 [doi]
• Closit: Clipped-Regime Posit Quantization for Edge-Friendly Vision TransformersSungsoo Han, Dahun Choi, Hyun Kim. 1-5 [doi]
• Sparsity-Gated Fp16 Mac Pipeline for Energyefficient Edram-Based Neural InferenceAkshay Kumar Sharma, Kyung Ki Kim. 1-4 [doi]
• A 16-Channel TDM Spectral Feature Extraction Using IIR Filter for Closed-Loop NeuromodulationTarun Choudhary, Lakshmi Iyer, Laxmeesha Somappa. 1-5 [doi]
• Memory and Energy Savings in the FPGA Implementation of Keyword Spotting with Stream ProcessingYuto Tada, Masanori Hashimoto, Makoto Miyamura, Xu Bai, Toshitsugu Sakamoto, Hiroyuki Ochi. 1-5 [doi]
• A Continuous-Wave/Frequency-Domain Reconfigurable Light-Sensing Readout Circuit for Functional Biomedical Imaging ApplicationWenzhe Qin, Huanyu You, Sibo Peng, Xiafan Gu, Eva Guttmann-Flury, Jiajun Yuan, Jian Zhao. 1-5 [doi]
• A DL-MRBL Scheme with Variation-Resilient Timing for Wide Voltage STT-MRAMRuiqi Zhang, Shuyu Wang, Haoran Du, Hao Cai 0001. 1-5 [doi]
• CoRN-LN: Compressed Reciprocal Newton Method for Efficient Layer NormalizationDawon Choi, Hana Kim, Ji-Hoon Kim. 1-5 [doi]
• A 2-4GHz Wideband Transmitter Front-End for FMCW Through-Wall Radar ApplicationsYunqi Yang, Haoyu Shen, Hao Lei, Zhigang Fu, Pengcheng Wang, Yilin Xu, Fanxun Cai, Xiao Fang, Hui Zhang. 1-5 [doi]
• Development of a Knee Rehabilitation Device in Compliance with Medical Device Standard ISO 13485Kiattisak Sengchuai, Watcharin Tayati, Dujdow Buranapanichkit, Apidet Booranawong, Nattha Jindapetch. 1-3 [doi]
• A 56 Gb/s PAM-4 CDR Circuit Using Middle Transition Masking and Integrated Bit Decoding SchemesSeung-Gyun Kim, Won Young Lee. 1-5 [doi]
• Design of Low-Spur Sub-Sampling PLL Employing a Passive Gain-Boosting Isolated SSPDYanlong Cai, Wenhui Liao, Yao Jiang, Ke Chen, Bi-Wu, Chenggang Yan. 1-5 [doi]
• Monolithic Hybrid-3D Standard Cell Library with Sandwiched Inter-Metal Layer for 3D Digital Computation-in-Memory CircuitsChieh-Ling Lee, Chu-Hsiu Hsu, Chih-Chao Yang, Chang-Hong Shen, Kuan-Neng Chen, Po-Tsang Huang, Chenming Hu. 1-5 [doi]
• A Multichannel Photoplethysmography Pipeline with Signal Quality Assessment for Robust Respiratory Rate EstimationJeffrey Chow, Nur Ahmadi, Trio Adiono, Fariska Zakhralativa Ruskanda. 1-5 [doi]
• FaceLiVT: Energy Efficient Face Recognition with Linear Vision Transformer for Limited Resource DeviceNovendra Setyawan, Jun-Xian Gu, Chi-Chia Sun, Mao-Hsiu Hsu, Wen-Kai Kuo, Chung-An Shen, Jun-Wei Hsieh. 1-5 [doi]
• Inter-Spike Interval Analysis of a Spiking Neuron Reduced to Piecewise-Constant DynamicsYuta Morimitsu, Tadashi Tsubone. 1-4 [doi]
• Pose-Based Video Sign Language Recognition on Edge Devices Using Deep Neural NetworksErik Tang. 1-5 [doi]
• A Low-Voltage DTMOS-Based Grounded Synthetic Inductor Using MOS-C TechniqueRuchita Gupta, Bhawna Aggarwal, Maneesha Gupta. 1-5 [doi]
• A Low-Power Bidirectional Clamping Circuit using Current-Starved Inverter and Current MirrorNarala Venkateswarlu, Gajendranath Chowdary. 1-5 [doi]
• Design of Dual-Frequency Load-Independent Class-E InverterYinchen Xie, Wenqi Zhu, Yutaro Komiyama, Ayano Komanaka, Akihiro Konishi, Kien Nguyen 0002, Hiroo Sekiya. 1-5 [doi]
• A Low Power, Bandwidth Enhanced, Negative-R Assisted Fourth Order Active-RC FilterSayyad Arif, Nagaveni S, Soumya Gupta, Manjunath Kareppagoudr. 1-5 [doi]
• A 28Nm Floating-Point SRAM-Based CIM Macro with Shifting-in-Memory Exponent Normalization and Mantissa AlignmentZhiting Lin, Yang Yang 0025, Miao Long, Hao Li, Rongtao Li, Wenqiang Zhang, Xin Wang, Qiang Zhao 0007, Xiulong Wu, Yu Liu 0113. 1-5 [doi]
• A 1.86ppm/°C CMOS-Only Voltage Reference with 20mA Load Driving CapabilityHuiqi Chen, Zhaonan Lu, Zili Zhou, Jiankao Pan, Shuang Song 0003, Menglian Zhao. 1-5 [doi]
• A 17.0-ENOB 400Hz-BW MASH 2-1 ADC with a Time-Multiplexed Nested SDM QuantizerZhengzhe Jia, Xinyu Xie, Zeyu Cai. 1-5 [doi]
• A Hardware-Efficient Approximate LMS-FFE for PAM4 Optical Communication SystemsYunjie Zhao, Hongfei Sun, Rong Wu, Ke Chen, Bi-Wu, Chenggang Yan. 1-5 [doi]
• Power Amplifier-Voltage Cotrolled Oscillator with Mixer for Millimeter-Wave Transmitter LinearizationWen Cheng Lai. 1-4 [doi]
• Performance Evaluation and Optimization of the Sampling Process of an Neuropredictive SAR ADCAlexander Spielberger, Lucas Spitzkopf, Albert-Marcel Schrotz, Christof Pfannenmüller, Robert Weigel, Norman Franchi. 1-5 [doi]
• Rigorous Verification of Implicit Poincaré Map Generated by a Sinusoidally Forced Continuous Piecewise Linear CircuitHideaki Okazaki, Naohiko Inaba. 1-5 [doi]