Table of Contents

• A transformative approach to the partitioning of processor arraysJürgen Teich, Lothar Thiele. 4-20 [doi]
• Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughputPhu Hoang, Jan M. Rabaey. 21-36 [doi]
• Linear scheduling is close to optimalityAlain Darte, Leonid Khachiyan, Yves Robert. 37-46 [doi]
• On systolic mapping of multi-stage algorithmsYin-Tsung Hwang, Yu Hen Hu. 47-61 [doi]
• A projective geometry architecture for scientific computationBharadwaj S. Amrutur, Rajeev Joshi, Narendra K. Karmarkar. 64-80 [doi]
• On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speedsGlenn Jennings. 81-88 [doi]
• On partitioning of multistage algorithms and design of intermediate memoriesMatthias Sauer 0001, Ernst G. Bernard, Josef A. Nossek. 89-101 [doi]
• A reconfigurable processor array with routing LSIs and general purpose DSPsJacob Levison, Ichiro Kuroda, Takao Nishitani. 102-116 [doi]
• Synthesis of application-specific multiprocessor systems including memory componentsShiv Prakash, Alice C. Parker. 118-132 [doi]
• An integrated system for rapid prototyping of high performance algorithm specific data pathsD. C. Chen, Lisa M. Guerra, E. H. Ng, Miodrag Potkonjak, D. P. Schultz, Jan M. Rabaey. 134-148 [doi]
• ARREST: an interactive graphic analysis tool for VLSI arraysWayne Burleson, Bongjin Jung. 149-162 [doi]
• Pipelining: just another transformationMiodrag Potkonjak, Jan M. Rabaey. 163-175 [doi]
• SPERT: a VLIW/SIMD microprocessor for artificial neural network computationsKrste Asanovic, James Beck, Brian Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek. 178-190 [doi]
• Implementing a family of high performance, micrograined architecturesRobert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa. 191-205 [doi]
• Deterministic Boltzmann machine VLSI can be scaled using multi-chip modulesMichael Murray, James B. Burr, David G. Stork, Ming-Tak Leung, Kan Boonyanit, Gregory J. Wolff, Allen M. Peterson. 206-217 [doi]
• Discrete wavelet transforms in VLSIMohan Vishwanath, Robert Michael Owens, Mary Jane Irwin. 218-229 [doi]
• Algorithms and architectures for high performance recursive filteringStephen E. McQuillan, John V. McCanny. 230-244 [doi]
• On metrics of 'super performance' [signal processing systems]Y. S. Wu. 248-256 [doi]
• Advanced technology for improved signal processor efficiencyEarl E. Swartzlander Jr.. 257-268 [doi]
• Some low power implementations of DSP algorithmsJoseph B. Evans, Bede Liu. 269-276 [doi]
• MUSE-a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer scale integrationCharles M. Rader. 277-291 [doi]
• Heterogeneous digital signal processing systems for sonarT. E. Curtis. 294-302 [doi]
• Constant capacity signal flow signal processor architecture benchmarkHans Habereder, R. Loyd Harrison. 303-315 [doi]
• Application and packaging of the AT&T DSP3 parallel signal processorRichard R. Shively, Les J. Wu. 316-326 [doi]
• Architecture and realization of a multi signal processor systemAnton Gunzinger, Urs A. Müller, Walter Scott, Bernhard Bäumle, Peter Kohler, Walter Guggenbühl. 327-340 [doi]
• The Sarnoff Engine: a massively parallel computer for high definition system simulationStan Knight, Danny Chin, Herb Taylor, J. Peters. 342-356 [doi]
• High speed bit-level pipelined architectures for redundant CORDIC implementationHerbert Dawid, Heinrich Meyr. 358-372 [doi]
• High-speed VLSI architectures for soft-output Viterbi decodingOlaf J. Joeressen, Martin Vaupel, Heinrich Meyr. 373-384 [doi]
• An architecture for tree search based vector quantization for single chip implementationHeonchul Park, Viktor K. Prasanna, Cho-Li Wang. 385-399 [doi]
• A systolic array chip for robot inverse dynamics computationMahib Rahman, David G. Meyer. 400-414 [doi]
• A method to synthesize modular systolic arrays with local broadcast facilityTanguy Risset. 415-428 [doi]
• A systolic rank revealing QR algorithmFlavio Lorenzelli, Kung Yao, Tony F. Chan, Per Christian Hansen. 430-444 [doi]
• Interval-related problems on reconfigurable meshesStephan Olariu, James L. Schwing, Jingyuan Zhang. 445-455 [doi]
• A parallel sorting algorithm on an eight-neighbor processor arrayKuninobo Tanno, Toshihiro Takeda, Susumu Horoguchi. 456-468 [doi]
• Fault tolerant matrix triangularization and solution of linear systems of equationsPatrick Fitzpatrick, Colin C. Murphy. 469-480 [doi]
• Systolic architectures for finite-state vector quantizationRavi K. Kolagotla, Shu-sun Yu, Joseph F. JáJá. 481-495 [doi]
• Matrix computations in arrays of DSPsJaime Moreno, Mario Medina. 496-510 [doi]
• MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphsDinh Lê, Milos D. Ercegovac, Tomás Lang, Jaime H. Moreno. 511-525 [doi]
• Determining longest common subsequences of two sequences on a linear array of processorsAmar Mukherjee. 526-537 [doi]
• Associative information processing: algorithms and systemWerner Pöchmüller, Andreas König 0001, Manfred Glesner. 538-550 [doi]
• Parallel architecture for a pel-recursive motion estimation algorithmEmmanuel D. Frimout, Johannes N. Driessen, Ed F. Deprettere. 551-558 [doi]
• Mapping locally recursive SEGs upon a multiprocessor system in a ring networkWonyong Sung, Sanjit K. Mitra, Ki-Il Kum. 560-573 [doi]
• Transformation techniques for serial array designWayne W. C. Luk. 574-588 [doi]
• Compilation of narrowband spectral detection systems for linear MIMD machinesHarry Printz. 589-603 [doi]
• Programming systolic arraysRichard Hughey. 604-618 [doi]
• Scheduling partitions in systolic algorithmsAlvaro Suárez, José M. Llabería, Agustín Fernández. 619-633 [doi]
• Optimal design of lower dimensional processor arrays for uniform recurrencesKumar N. Ganapathy, Benjamin W. Wah. 636-648 [doi]
• Efficient scheduling methods for partitioned systolic algorithmsPrashanth Kuchibhotla, Bhaskar D. Rao. 649-663 [doi]
• Fully static multiprocessor realization for real-time recursive DSP algorithmsDuen-Jeng Wang, Yu Hen Hu. 664-678 [doi]
• High level software synthesis for signal processing systemsSebastian Ritz, Matthias Pankert, Heinrich Meyr. 679-693 [doi]