Table of Contents

• Convergence of design and fabrication technologies, a key enabler for HW-SW integrationAhmed Amine Jerraya. 3 [doi]
• The light at the end of the CMOS tunnelSani R. Nassif. 4-9 [doi]
• Dynamic code mapping for limited local memory systemsSeung Chul Jung, Aviral Shrivastava, Ke Bai. 13-20 [doi]
• Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband EngineWeijia Che, Karam S. Chatha. 21-28 [doi]
• Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUsKeisuke Dohi, Khaled Benkrid, Cheng Ling, Tsuyoshi Hamada, Yuichiro Shibata. 29-36 [doi]
• ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processorsDhara Dave, Christos Strydis, Georgi Gaydadjiev. 39-46 [doi]
• Design space exploration of parametric pipelined designsAdrien Le Masle, Wayne Luk. 47-54 [doi]
• Design space exploration for an embedded processor with flexible datapath interconnectTung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors. 55-62 [doi]
• Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware acceleratorsTobias Beisel, Manuel Niekamp, Christian Plessl. 65-72 [doi]
• Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnectsSujay Deb, Amlan Ganguly, Kevin Chang, Partha Pratim Pande, Benjamin Belzer, Deuk Heo. 73-80 [doi]
• A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system designAmelia W. Azman, Abbas Bigdeli, Yasir Mohd-Mustafah, Morteza Biglari-Abhari, Brian C. Lovell. 81-88 [doi]
• An optimized NoC architecture for accelerating TSP kernels in breakpoint median problemTurbo Majumder, Souradip Sarkar, Partha Pande, Ananth Kalyanaraman. 89-96 [doi]
• A formal specification of fault-tolerance in prospecting asteroid mission with Reactive Autonomie Systems FrameworkHeng Kuang, Olga Ormandjieva, Stan Klasa, Jamal Bentahar. 99-106 [doi]
• Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computingYocheved Dotan, Orgad Chen, Gil Katz. 107-114 [doi]
• Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGAGaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin. 115-122 [doi]
• Modeling and synthesis of communication subsystems for loop accelerator pipelinesHritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert. 125-132 [doi]
• Design of throughput-optimized arrays from recurrence abstractionsArpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain. 133-140 [doi]
• A C++-embedded Domain-Specific Language for programming the MORA soft processor arrayWim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit. 141-148 [doi]
• A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architecturesGuillermo Payá Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch. 151-158 [doi]
• Dual-purpose custom instruction identification algorithm based on Particle Swarm OptimizationMehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori. 159-166 [doi]
• Combined scheduling and instruction selection for processors with reconfigurable cell fabricAntoine Floch, Christophe Wolinski, Krzysztof Kuchcinski. 167-174 [doi]
• Completeness of automatically generated instruction selectorsFlorian Brandner. 175-182 [doi]
• Implementation of binary edwards curves for very-constrained devicesUnal Kocabas, Junfeng Fan, Ingrid Verbauwhede. 185-191 [doi]
• Elliptic Curve point multiplication on GPUsSamuel Antao, Jean-Claude Bajard, Leonel Sousa. 192-199 [doi]
• Newton-Raphson algorithms for floating-point division using an FMANicolas Louvet, Jean-Michel Muller, Adrien Panhaleux. 200-207 [doi]
• An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbersDavid B. Thomas, Wayne Luk. 208-215 [doi]
• Automatic generation of polynomial-based hardware architectures for function evaluationFlorent de Dinechin, Mioara Joldes, Bogdan Pasca. 216-222 [doi]
• A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applicationsBo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng. 225-232 [doi]
• High parallel variation Banyan network based permutation network for reconfigurable LDPC decoderXiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto. 233-238 [doi]
• A high efficient memory architecture for H.264/AVC motion compensationChunshu Li, Kai Huang, Xiaolang Yan, Jiong Feng, De Ma, Haitong Ge. 239-245 [doi]
• FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidthKazuya Katahira, Kentaro Sano, Satoru Yamamoto. 246-253 [doi]
• Power dissipation challenges in multicore floating-point unitsWei Liu, Alberto Nannarelli. 257-264 [doi]
• On energy efficiency of reconfigurable systems with run-time partial reconfigurationShaoshan Liu, Richard Neil Pittman, Alessandro Form, Jean-Luc Gaudiot. 265-272 [doi]
• A GALS FFT processor with clock modulation for low-EMI applicationsXin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass. 273-278 [doi]
• Hardware-assisted middleware: Acceleration of garbage collection operationsJie Tang, Shaoshan Liu, Zhimin Gu, Xiao-Feng Li, Jean-Luc Gaudiot. 281-284 [doi]
• Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applicationsMohamed N. Hassan, Mohammed Benaissa, A. Kanakis. 285-288 [doi]
• An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computerOguzhan Atak, Abdullah Atalar. 289-292 [doi]
• Potential of using block floating point arithmetic in ASIP-based GNSS-receiversE. Tasdemir, Götz Kappen, Tobias G. Noll. 293-296 [doi]
• Area optimized H.264 Intra prediction architecture for 1080p HD resolutionJimit Shah, K. S. Raghunandan, Kuruvilla Varghese. 297-300 [doi]
• Memoryless RNS-to-binary converters for the {2:::n+1::: - 1, 2:::n:::, 2:::n::: - 1} moduli setKazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Cotofana. 301-304 [doi]
• A pipelined camellia architecture for compact hardware implementationElif Bilge Kavun, Tolga Yalçin. 305-308 [doi]
• General-purpose FPGA platform for efficient encryption and hashingJakub Szefer, Yu-Yuan Chen, Ruby B. Lee. 309-312 [doi]
• A compact FPGA-based architecture for elliptic curve cryptography over prime fieldsJo Vliegen, Nele Mentens, Jan Genoe, An Braeken, Serge Kubera, Abdellah Touhafi, Ingrid Verbauwhede. 313-316 [doi]
• Implementing decimal floating-point arithmetic through binary: Some suggestionsNicolas Brisebarre, Nicolas Louvet, Érik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, Milos D. Ercegovac. 317-320 [doi]
• A New approach in on-line task scheduling for reconfigurable computing systemsMaisam Mansub Bassiri, Hadi Shahriar Shahhoseini. 321-324 [doi]
• Exploring algorithmic trading in reconfigurable hardwareStephen Wray, Wayne Luk, Peter Pietzuch. 325-328 [doi]
• Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS toolChristophe Alias, Alain Darte, Alexandra Plesco. 329-332 [doi]
• Deadlock-avoidance for streaming applications with split-join structure: Two case studiesPeng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, Joseph M. Lancaster. 333-336 [doi]
• Customizing controller instruction sets for application-specific architecturesJian Li, David Dickin, Lesley Shannon. 337-340 [doi]
• Loop transformations for interface-based hierarchies IN SDF graphsJonathan Piat, Shuvra S. Bhattacharyya, Mickaël Raulet. 341-344 [doi]
• Code generation for hardware accelerated AESRaymond Manley, Paul Magrath, David Gregg. 345-348 [doi]
• Function flattening for lease-based, information-leak-free systemsXun Li, Mohit Tiwari, Timothy Sherwood, Frederic T. Chong. 349-352 [doi]