Abstract is missing.
- Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAsDavid Shah, Eddie Hung, Clifford Wolf, Serge Bazanski, Dan Gisselquist, Miodrag Milanovic. 1-4 [doi]
- EFCAD - An Embedded FPGA CAD Tool Flow for Enabling On-chip Self-CompilationKhoa Dang Pham, Malte Vesper, Dirk Koch, Eddie Hung. 5-8 [doi]
- Maverick: A Stand-Alone CAD Flow for Partially Reconfigurable FPGA ModulesDallon Glick, Jesse Grigg, Brent E. Nelson, Michael J. Wirthlin. 9-16 [doi]
- An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAsLiqiang Lu, JiaMing Xie, Ruirui Huang, Jiansong Zhang, Wei Lin, Yun Liang 0001. 17-25 [doi]
- LUTNet: Rethinking Inference in FPGA Soft LogicErwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides. 26-34 [doi]
- PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural NetworksSeyedRamin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong. 35-44 [doi]
- Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level ParallelismCheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo. 45-52 [doi]
- CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA RouterDries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt. 53-60 [doi]
- RapidRoute: Fast Assembly of Communication Structures for FPGA OverlaysLeo Liu, Jay Weng, Nachiket Kapre. 61-64 [doi]
- Generic Connectivity-Based CGRA Mapping via Integer Linear ProgrammingMatthew J. P. Walker, Jason Helge Anderson. 65-73 [doi]
- LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design ClosureEcenur Ustun, Shaojie Xiang, Jinny Gui, Cunxi Yu, Zhiru Zhang. 74-77 [doi]
- Memory Mapping for Multi-die FPGAsNils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev. 78-86 [doi]
- Impact of FPGA Architecture on Area and Performance of CGRA OverlaysIan Taras, Jason Helge Anderson. 87-95 [doi]
- An FPGA-Based BWT Accelerator for Bzip2 Data CompressionWeikang Qiao, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong. 96-99 [doi]
- π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation OptimizationShuzhen Qin, Qiang Liu, Bo Yu, Shaoshan Liu. 100-108 [doi]
- Deep Packet Inspection in FPGAs via Approximate Nondeterministic AutomataMilan Ceska 0001, Vojtech Havlena, Lukás Holík, Jan Korenek, Ondrej Lengál, Denis Matousek, Jirí Matousek 0002, Jakub Semric, Tomás Vojnar. 109-117 [doi]
- Active Stereo Vision with High Resolution on an FPGAMarc Pfeifer, Philipp M. Scholl, Rainer Voigt, Bernd Becker 0001. 118-126 [doi]
- Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPULicheng Guo, Jason Lau, Zhenyuan Ruan, Peng Wei 0004, Jason Cong. 127-135 [doi]
- Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory PlatformYu Wang, James C. Hoe, Eriko Nurvitadhi. 136-144 [doi]
- MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory CubeJialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha, Jonathan Ta, Jing Li. 145-153 [doi]
- Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow ControlGurshaant Singh Malik, Nachiket Kapre. 154-162 [doi]
- SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCsKonstantinos Iordanou, Oscar Palomar, John Mawer, Cosmin Gorgovan, Andy Nisbet, Mikel Luján. 163-171 [doi]
- Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGAZhe Lin 0007, Sharad Sinha, Wei Zhang. 172-180 [doi]
- T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor ComputationsNitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang, David H. Albonesi, Vivek Sarkar, Wenguang Chen, Paul Petersen, Geoff Lowney, Adam Herr, Christopher J. Hughes, Timothy G. Mattson, Pradeep Dubey. 181-189 [doi]
- SparseHD: Algorithm-Hardware Co-optimization for Efficient High-Dimensional ComputingMohsen Imani, Sahand Salamat, Behnam Khaleghi, Mohammad Samragh, Farinaz Koushanfar, Tajana Rosing. 190-198 [doi]
- Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNsEriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu. 199-207 [doi]
- Design Patterns for Code Reuse in HLS Packet Processing PipelinesHaggai Eran, Lior Zeno, Zsolt Istvan, Mark Silberstein. 208-217 [doi]
- Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis DesignJeferson Santiago da Silva, Francois-Raymond Boyer, J. M. Pierre Langlois. 218-226 [doi]
- Templatised Soft Floating-Point for High-Level SynthesisDavid B. Thomas. 227-235 [doi]
- Exploiting Irregular Memory Parallelism in Quasi-Stencils through Nonlinear TransformationJuan Escobedo, Mingjie Lin. 236-244 [doi]
- FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement ApplicationsTianqi Wang, Tong Geng, Xi Jin, Martin C. Herbordt. 245-253 [doi]
- Compressed Sensing MRI Reconstruction on Intel HARPv2Yushan Su, Michael Anderson, Jonathan I. Tamir, Michael Lustig, Kai Li. 254-257 [doi]
- GhostSZ: A Transparent FPGA-Accelerated Lossy Compression FrameworkQingqing Xiong, Rushi Patel, Chen Yang, Tong Geng, Anthony Skjellum, Martin C. Herbordt. 258-266 [doi]
- Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode FailuresMaheshwaran Ramesh Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer. 267-270 [doi]
- Fast Voltage Transients on FPGAs: Impact and Mitigation StrategiesLinda L. Shen, Ibrahim Ahmed 0001, Vaughn Betz. 271-279 [doi]
- FASE: FPGA Acceleration of Secure Function EvaluationSiam U. Hussain, Farinaz Koushanfar. 280-288 [doi]
- Rethinking Integer Divider Design for FPGA-Based Soft-ProcessorsEric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon. 289-297 [doi]
- High Precision, High Performance FPGA AddersMartin Langhammer, Bogdan Pasca, Gregg Baeckler. 298-306 [doi]
- Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable SystemsRafael Zamacola, Alberto Garcia Martinez, Javier Mora 0001, Andrés Otero, Eduardo de la Torre. 307 [doi]
- AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement LearningQijing Huang, Ameer Haj Ali, William Moses, John Xiang, Ion Stoica, Krste Asanovic, John Wawrzynek. 308 [doi]
- Efficient FPGA Floorplanning for Partial Reconfiguration-Based ApplicationsNorbert Deak, Octavian Cret, Horia Hedesiu. 309 [doi]
- Towards Prototyping and Acceleration of Java Programs onto Intel FPGAsMichail Papadimitriou, Juan Fumero, Athanasios Stratikopoulos, Christos Kotselidis. 310 [doi]
- Sonar: Writing Testbenches through PythonVarun Sharma, Naif Tarafdar, Paul Chow. 311 [doi]
- Raparo: Resource-Level Angle-Based Parallel Routing for FPGAsMinghua Shen, Nong Xiao. 312 [doi]
- Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based SystemsFrancesco Peverelli, Marco Rabozzi, Salvatore Cardamone, Emanuele Del Sozzo, Alex J. W. Thom, Marco D. Santambrogio, Lorenzo Di Tucci. 313 [doi]
- Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS ApplicationsMarco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio, Lorenzo Di Tucci. 314 [doi]
- Formalizing Loop-Carried Dependencies in Coq for High-Level SynthesisFlorian Faissole, George A. Constantinides, David Thomas. 315 [doi]
- Exploring the Random Network of Hodgkin and Huxley Neurons with Exponential Synaptic Conductances on OpenCL FPGA PlatformZheming Jin, Hal Finkel. 316 [doi]
- A Scalable OpenCL-Based FPGA Accelerator for YOLOv2Ke Xu, Xiaoyun Wang, Dong Wang. 317 [doi]
- Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic AnalysisKota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino. 318 [doi]
- SimBNN: A Similarity-Aware Binarized Neural Network Acceleration FrameworkCheng Fu, Shilin Zhu, Huili Chen, Farinaz Koushanfar, Hao Su, Jishen Zhao. 319 [doi]
- KPynq: A Work-Efficient Triangle-Inequality Based K-Means on FPGAYuke Wang, Zhaorui Zeng, Boyuan Feng, Lei Deng, Yufei Ding. 320 [doi]
- A High Throughput and Energy-Efficient Retina-Inspired Tone Mapping ProcessorLili Liu, Xiaoqiang Xiang, Yuxiang Xie, Yongjie Li, Bo Yan, Jun Zhou. 321 [doi]
- An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA PlatformSamah Rahamneh, Lina Sawalha. 322 [doi]
- Scalable P4 Deparser for Speeds Over 100 GbpsJakub Cabal, Pavel Benácek, Jana Foltova, Juraj Holub. 323 [doi]
- Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted DataSang-Woo Jun, Arvind Arvind. 324 [doi]
- Hybrid XML Parser Based on Software and Hardware Co-designZhe Pan, Xiaohong Jiang, Jian Wu, Xiang Li 0017. 325 [doi]
- Sorting Large Data Sets with FPGA-Accelerated SamplesortHan Chen, Sergey Madaminov, Michael Ferdman, Peter Milder. 326 [doi]
- Cost-Effective Energy Monitoring of a Zynq-Based Real-Time System Including Dual Gigabit EthernetMartin Geier, Dominik Faller, Marian Brändle, Samarjit Chakraborty. 327 [doi]
- Improved Techniques for Sensing Intra-Device Side Channel LeakageWilliam Hunter, Christopher McCarty, Lee Lerner. 328 [doi]
- Safe Task Interruption for FPGAsSameh Attia, Vaughn Betz. 329 [doi]
- OpenCL Kernel Vectorization on the CPU, GPU, and FPGA: A Case Study with Frequent Pattern CompressionZheming Jin, Hal Finkel. 330 [doi]
- A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot ApplicationsAtsutake Kosuge, Keisuke Yamamoto, Yukinori Akamine, Taizo Yamawaki, Takashi Oshima. 331 [doi]
- Monobit Wideband Receiver with Integrated Dithering in FPGADan Pritsker, Colman Cheung. 332 [doi]
- An FPGA-Based Computing Infrastructure Tailored to Efficiently Scaffold Genome SequencesAlberto Zeni, Matteo Crespi, Lorenzo Di Tucci, Marco D. Santambrogio. 333 [doi]
- FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured GraphsGlenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks 0001, Gu-Yeon Wei. 334 [doi]
- A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution ModelJian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee. 335 [doi]
- Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA PlatformsMurad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers. 336 [doi]
- Large-Scale and High-Throughput QR Decomposition on an FPGADajung Lee, Andrei Hagiescu, Dan Pritsker. 337 [doi]
- Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design ConstraintsSergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, Lorena Anghel, Mircea Stan. 338 [doi]