Abstract is missing.
- High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG CompressionHiroki Nakahara, Zhiqiang Que, Wayne Luk. 1-9 [doi]
- Optimizing Reconfigurable Recurrent Neural NetworksZhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk. 10-18 [doi]
- Accelerating Proximal Policy Optimization on CPU-FPGA Heterogeneous PlatformsYuan Meng, Sanmukh R. Kuppannagari, Viktor K. Prasanna. 19-27 [doi]
- Evaluating Low-Memory GEMMs for Convolutional Neural Network Inference on FPGAsWentai Zhang, Ming Jiang 0001, Guojie Luo. 28-32 [doi]
- CNN-based Feature-point Extraction for Real-time Visual SLAM on Embedded FPGAZhilin Xu, Jincheng Yu, Chao Yu, Hao Shen, Yu Wang, Huazhong Yang. 33-37 [doi]
- Corundum: An Open-Source 100-Gbps NicAlex Forencich, Alex C. Snoeren, George Porter, George Papen. 38-46 [doi]
- FFShark: A 100G FPGA Implementation of BPF Filtering for WiresharkJuan Camilo Vega, Marco Antonio Merlini, Paul Chow. 47-55 [doi]
- Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption SchemeSunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar. 56-64 [doi]
- Power-hammering through Glitch Amplification - Attacks and MitigationKaspar Matas, Tuan Minh La, Khoa Dang Pham, Dirk Koch. 65-69 [doi]
- Exploring The Impact Of Switch Arity On Butterfly Fat Tree Fpga NocsIan Lang, Ziqiang Huang, Nachiket Kapre. 70-74 [doi]
- Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAsLukas Sommer, Lukas Weber, Martin Kumm, Andreas Koch 0001. 75-83 [doi]
- High Density 8-Bit Multiplier Systolic Arrays For FpgaMartin Langhammer, Sergey Gribok, Gregg Baeckler. 84-92 [doi]
- Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP ApplicationsS. Rasoul Faraji, Pierre Abillama, Kia Bazargan. 93-101 [doi]
- Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the CloudShulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang. 102-110 [doi]
- Shuhai: Benchmarking High Bandwidth Memory On FPGASZeke Wang, Hongjing Huang, Jie Zhang, Gustavo Alonso. 111-119 [doi]
- Exploring Writeback Designs for Efficiently Leveraging Parallel-Execution Units in FPGA-Based Soft-ProcessorsEric Matthews, YuHui Gao, Lesley Shannon. 120-128 [doi]
- Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoCFrancesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgio C. Buttazzo. 129-137 [doi]
- Grapefruit: An Open-Source, Full-Stack, and Customizable Automata Processing on FPGAsReza Rahimi, Elaheh Sadredini, Mircea Stan, Kevin Skadron. 138-147 [doi]
- FP-AMG: FPGA-Based Acceleration Framework for Algebraic Multigrid SolversPouya Haghi, Tong Geng, Anqi Guo, Tianqi Wang, Martin C. Herbordt. 148-156 [doi]
- Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKitMichael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong. 157-166 [doi]
- A Turbo Maximum-a-Posteriori Equalizer for Faster-than-Nyquist ApplicationsMohamed Omran Matar, Mrinmoy Jana, Jeebak Mitra, Lutz Lampe, Mieszko Lis. 167-171 [doi]
- FPGA-accelerated Automatic Alignment for Three-dimensional TomographyShuang Wen, Guojie Luo. 172-176 [doi]
- Artisan: a Meta-Programming Approach For Codifying Optimisation StrategiesJessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman. 177-185 [doi]
- Hierarchical Modelling of Generators in Design-Space ExplorationCharles Lo, Paul Chow. 186-194 [doi]
- Investigating Performance Losses in High-Level Synthesis for Stencil ComputationsWesson Altoyan, Juan J. Alonso. 195-203 [doi]
- Proposing a Fast and Scalable Systolic Array for Matrix MultiplicationBahar Asgari, Ramyad Hadidi, Hyesoon Kim. 204 [doi]
- An Automated Tool for Design Space Exploration of Matrix Vector Multiplication (MVM) Kernels Using OpenCL Based Implementation on FPGAsJannatun Naher, Clay Gloster, Christopher C. Doss, Shrikant S. Jadhav. 205 [doi]
- Fast Arithmetic Hardware Library For RLWE-Based Homomorphic EncryptionRashmi Agrawal, Lake Bu, Michel A. Kinsy. 206 [doi]
- Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In TestabilityAyan Palchaudhuri, Anindya Sundar Dhar. 207 [doi]
- TBOX-Based Mask Scrambling Against SCAJoão Carlos Resende, Ricardo J. R. Maçãs, Ricardo Chaves. 208 [doi]
- FPGA Implementation of Post-Quantum DME CryptosystemJosé Luis Imaña, Ignacio Luengo. 209 [doi]
- A Dynamic Frequency Scaling Framework Against Reliability and Security Issues in Multi-tenant FPGAYukui Luo, Xiaolin Xu. 210 [doi]
- SHIP: Storage for Hybrid Interconnected ProcessorsJuan Camilo Vega, Qianfeng Clark Shen, Paul Chow. 211 [doi]
- RISC-V Barrel Processor for Accelerator ControlMohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David. 212 [doi]
- Update Latency Optimization of Packet Classification for SDN Switch on FPGAChenglong Li, Tao Li, Junnan Li, Zilin Shi, Baosheng Wang. 213 [doi]
- Accommodating Multi-Tenant FPGAs in the CloudJoel Mandebi Mbongue, Christophe Bobda. 214 [doi]
- Accelerating MPI Collectives with FPGAs in the Network and Novel Communicator SupportQingqing Xiong, Chen Yang, Pouya Haghi, Anthony Skjellum, Martin C. Herbordt. 215 [doi]
- MeXT-SE: A System-Level Design Tool to Transparently Generate Secure MPSoCMd Jubaer Hossain Pantho, Christophe Bobda. 216 [doi]
- Early-stage Automated Identification Tool for Shared AcceleratorsParnian Mokri, Mark Hempstead. 217 [doi]
- An Analytical Model of Memory-Bound Applications Compiled with High Level SynthesisMaria Angelica Davila Guzman, Ruben Gran Tejero, María Villarroya-Gaudó, Darío Suárez Gracia. 218 [doi]
- FPGA Virtualization for Deprecated DevicesIan D. Taras, Andrew G. Schmidt. 219 [doi]
- ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing ClustersBurkhard Ringlein, François Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey. 220 [doi]
- Designing Domain Specific Computing SystemsAnthony M. Cabrera, Roger D. Chamberlain. 221 [doi]
- Improving the Availability of Secure Space Links through the Partial Reconfiguration of FPGAsEmmanuel Lesser. 222 [doi]
- An FPGA-Optimized Architecture of Real-time Farneback Optical FlowZhe Pan, Yuruo Jin, Xiaohong Jiang, Jian Wu. 223 [doi]
- High-Performance Parallel Radix Sort on FPGABashar Romanous, Mohammadreza Rezvani, Junjie Huang, Daniel Wong, Evangelos E. Papalexakis, Vassilis J. Tsotras, Walid A. Najjar. 224 [doi]
- FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural NetworksHaoyan Liu, Atiyehsadat Panahi, David Andrews, Alexander Nelson. 225 [doi]
- Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level SpecificationsOscar Ferraz, Srinivasan Subramaniyan, Guohui Wang, Joseph R. Cavallaro, Gabriel Falcão, Madhura Purnaprajna. 226 [doi]
- A Quaternary FPGA Architecture Using Floating Gate MemoriesAyokunle Fadamiro, Pouyan Rezaie, Christopher Harris, Spencer Millican. 227 [doi]
- Rotary Register File: A Micro-Architectural Primitive on FPGAReza Nakhjavani, Jianwen Zhu. 228 [doi]
- Tiny On-Chip Memory Realization of Weight Sparseness Split-CNNs on Low-end FPGAsAkira Jinguji, Shimpei Sato, Hiroki Nakahara. 229 [doi]
- An Efficient FPGA-based Architecture for Contractive AutoencodersMadis Kerner, Kalle Tammemäe, Jaan Raik, Thomas Hollstein. 230 [doi]
- Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge ComputingAkshay Dua, Yixing Li, Fengbo Ren. 231 [doi]
- Explore Efficient LUT-based Architecture for Quantized Convolutional Neural Networks on FPGAYanpeng Cao, Chengcheng Wang, Yongming Tang. 232 [doi]
- Realization of Quantized Neural Network for Super-resolution on PYNQFeng Yu, Yanpeng Cao, Yongming Tang. 233 [doi]
- Scalable Full Hardware Logic Architecture for Gradient Boosted Tree TrainingTamon Sadasue, Tsuyoshi Isshiki. 234 [doi]
- Optimized Distribution of an Accelerated Convolutional Neural Network across Multiple FPGAsAlaa Maarouf, Nour El Droubi, Raghid Morcel, Hazem M. Hajj, Mazen A. R. Saghir, Haitham Akkary. 235 [doi]
- SqueezeJet-3: An Accelerator Utilizing FPGA MPSoCs for Edge CNN ApplicationsPanagiotis Mousouliotis, Ioannis Papaefstathiou, Loukas Petrou. 236 [doi]
- Automatic Generation of FPGA Kernels From Open Format CNN ModelsDimitrios Danopoulos, Christoforos Kachris, Dimitrios Soudris. 237 [doi]
- High-Throughput DNN Inference with LogicNetsYaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, Michaela Blott. 238 [doi]
- AIgean: An Open Framework for Machine Learning on Heterogeneous ClustersNaif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow. 239 [doi]
- FPGA Based High-Throughput Real-Time Feature Extraction for Modulation ClassificationJoshua Mack, Ali Akoglu. 240 [doi]
- Accelerating Large Scale GCN Inference on FPGABingyi Zhang, Hanqing Zeng, Viktor K. Prasanna. 241 [doi]
- EASpiNN: Effective Automated Spiking Neural Network Evaluation on FPGASathish Panchapakesan, Zhenman Fang, Nitin Chandrachoodan. 242 [doi]
- A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNsNing Li, Leibo Liu, Shaojun Wei, Shouyi Yin. 243 [doi]