Abstract is missing.
- The effect of LUT and cluster size on deep-submicron FPGA performance and densityElias Ahmed, Jonathan Rose. 3-12 [doi]
- Programmable memory blocks supporting content-addressable memoryFrank Heile, Andrew Leaver, Kerry Veenstra. 13-21 [doi]
- A novel high throughput reconfigurable FPGA architectureAmit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska. 22-29 [doi]
- An FPGA implementation and performance evaluation of the Serpent block cipherAdam J. Elbirt, Christof Paar. 33-40 [doi]
- Technology mapping for k/m-macrocell based FPGAsJason Cong, Hui Huang, Xin Yuan. 51-59 [doi]
- Technology mapping issues for an FPGA with lookup tables and PLA-like blocksAlireza Kaviani, Stephen Dean Brown. 60-66 [doi]
- Heterogeneous technology mapping for FPGAs with dual-port embedded memory arraysSteven J. E. Wilton. 67-74 [doi]
- Synthesis for FPGAs with embedded memory blocksJason Cong, Kenneth Yan. 75-82 [doi]
- A C compiler for a processor with a reconfigurable functional unitZhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee. 95-100 [doi]
- The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designersHerman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate. 101 [doi]
- A representation for dynamic graphs in reconfigurable hardware and its application to fundamental graph algorithmsLorenz Huelsbergen. 105-115 [doi]
- The application of genetic algorithms to the design of reconfigurable reasoning VLSI chipsMoritoshi Yasunaga, Jung Hwan Kim, Ikuo Yoshihara. 116-125 [doi]
- A benchmark suite for evaluating configurable computing systems--status, reflections, and future directionsS. Kumar, Luiz Pires, Subburajan Ponnuswamy, C. Nanavati, J. Golusky, M. Vojta, S. Wadi, D. Pandalai, Henk A. E. Spaanenburg. 126-134 [doi]
- Field programmable port extender (FPX) for distributed routing and queuingJohn W. Lockwood, Jonathan S. Turner, David E. Taylor. 137-144 [doi]
- Implementing a RAKE receiver for wireless communications on an FPGA-based computer systemAli M. Shankiti, Miriam Leeser. 145-151 [doi]
- Generating highly-routable sparse crossbars for PLDsGuy G. Lemieux, Paul Leventis, David M. Lewis. 155-164 [doi]
- New parallelization and convergence results for NC: a negotiation-based FPGA routerPak K. Chan, Martine D. F. Schlag. 165-174 [doi]
- Automatic generation of FPGA routing architectures from high-level descriptionsVaughn Betz, Jonathan Rose. 175-184 [doi]
- Tolerating operational faults in cluster-based FPGAsVijay Lakamraju, Russell Tessier. 187-194 [doi]
- Power estimation approach for SRAM-based FPGAsKarlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel. 195-202 [doi]
- Timing-driven placement for FPGAsAlexander Marquardt, Vaughn Betz, Jonathan Rose. 203-213 [doi]
- Algorithm analysis and mapping environment for adaptive computing systems (poster abstract)Eric K. Pauer, Paul D. Fiore, John M. Smith, Cory S. Myers. 217 [doi]
- Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract)Yu-Chung Lin, Su-Feng Tseng, Tsai-Ming Hsieh. 217 [doi]
- Coarse-grained carry architecture for FPGA (poster abstract)Hyuk-Jun Lee, Michael J. Flynn. 217 [doi]
- Determining the optimum extended instruction-set architecture for application specific reconfigurable VLIW CPUs (poster abstract)Cesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami. 218 [doi]
- An FPGA-based genetic algorithm machine (poster abstract)Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura. 218 [doi]
- FPGA implementation and analysis of image restorationF. S. Ogrenci, Aggelos K. Katsaggelos, Majid Sarrafzadeh. 219 [doi]
- Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract)Michael J. Wirthlin, Paul Graham. 219 [doi]
- FPGA clock management for low power applications (poster abstract)Ian Brynjolfson, Zeljko Zilic. 219 [doi]
- Novel hardware-software architecture for the recursive merge filtering algorithm (poster abstract)Piyush Jamkhandi, Amar Mukherjee, Kunal Mukherjee, Robert Franceschini. 220 [doi]
- Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumptionAndrés D. García, Jean-Luc Danger, Wayne P. Burleson. 220 [doi]
- Real-time, frame-rate face detection on a configurable hardware system (poster abstract)Rob McCready, Jonathan Rose. 221 [doi]
- Scalable interconnect and power distribution for island-style FPGAs (poster abstract)Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari. 221 [doi]
- Reconfigurable target recognition system (poster abstract)Gábor Szedö, Sandeep Neema, Jason Scott, Ted Bapty. 221 [doi]
- Virtualization of FPGA via segmentation (poster abstract)William Fornaciari, Vincenzo Piuri, Luigi Ripamonti. 222 [doi]
- Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract)Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger. 222 [doi]