Table of Contents

• Cognitive Data-Centric SystemsLeland Chang. 1 [doi]
• Green Computing: New Challenges and OpportunitiesAlex K. Jones. 3 [doi]
• FPGAs in the Datacenter: Combining the Worlds of Hardware and Software DevelopmentAndrew Putnam. 5 [doi]
• Internet-of-Medical-ThingsNiraj K. Jha. 7 [doi]
• Designing Really Big Value IdeasAlex Bruton. 9 [doi]
• Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based CircuitsPilin Junsangsri, Fabrizio Lombardi, Salin Junsangsri, Martin Margala. 11-16 [doi]
• VaLHALLA: Variable Latency History Aware Local-carry Lazy AdderAli Murat Gok, Nikos Hardavellas. 17-22 [doi]
• Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI DeviceHao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao. 23-28 [doi]
• A Mixed-Size Monolithic 3D Placer with 2D Layout InheritanceXu He, Yao Wang 0002, Yang Guo, Sorin Cotofana. 29-34 [doi]
• LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized NetworksRuizhou Ding, Zeye Dexter Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton. 35-40 [doi]
• Design of a Flash-based Circuit for Multi-valued LogicMonther Abusultan, Sunil P. Khatri. 41-46 [doi]
• Design of Approximate Logarithmic MultipliersWeiqiang Liu, Jiahua Xu, Danye Wang, Fabrizio Lombardi. 47-52 [doi]
• Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic SystemsAmr M. S. Tosson, Shimeng Yu, Mohab Anis, Lan Wei. 53-58 [doi]
• A Spin-Orbit Torque based Cellular Neural Network (CNN) ArchitectureYu Bai, Sharon Hu, Ronald F. DeMara, Mingjie Lin. 59-64 [doi]
• PreNoc: Neural Network based Predictive Routing for Network-on-Chip ArchitecturesMichel A. Kinsy, Shreeya Khadka, Mihailo Isakov. 65-70 [doi]
• A Domain-Specific Language and Compiler for Computation-in-Memory SkeletonsJintao Yu, Tom Hogervorst, Razvan Nane. 71-76 [doi]
• Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion DevicesShaahin Angizi, Zhezhi He, Deliang Fan. 77-82 [doi]
• Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data EncryptionZhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan. 83-88 [doi]
• Evaluating Data Resilience in CNNs from an Approximate Memory PerspectiveYuanchang Chen, Yizhe Zhu, Fei Qiao, Jie Han, Yuansheng Liu, Huazhong Yang. 89-94 [doi]
• A Robust C-element Design with Enhanced Metastability PerformanceKinshuk Sharma, Sunil Khatri. 95-100 [doi]
• Circuit Level Design of a Hardware Hash Unit for use in Modern MicroprocessorsAbbas Fairouz, Monther Abusultan, Sunil P. Khatri. 101-106 [doi]
• DELCA: DVFS Efficient Low Cost Multicore ArchitectureShoumik Maiti, Sudeep Pasricha. 107-112 [doi]
• EEAL: Processors' Performance Enhancement Through Early Execution of Aliased LoadsAbhishek Rajgadia, Newton, Virendra Singh. 113-118 [doi]
• Performance-Aware Resource Management of Multi-Threaded Applications on Many-Core SystemsDaniel Olsen, Iraklis Anagnostopoulos. 119-124 [doi]
• Under-the-Cell Routing to Improve ManufacturabilityAlex Vidal-Obiols, Jordi Cortadella, Jordi Petit. 125-130 [doi]
• Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry ChainsZhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon. 131-136 [doi]
• Redundant Via Insertion with Cut Optimization for Self-Aligned Double PatterningYoungsoo Song, Jinwook Jung, Youngsoo Shin. 137-142 [doi]
• Boolean Decomposition for AIG OptimizationLucas Machado, Jordi Cortadella. 143-148 [doi]
• Mixed-Cell-Height Standard Cell Placement LegalizationChung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak. 149-154 [doi]
• Covert Timing Channels Exploiting Non-Uniform Memory Access based ArchitecturesFan Yao, Guru Venkataramani, Milos Doroslovacki. 155-160 [doi]
• A Low-Cost GPS Spoofing Detector Design for Internet of Things (IoT) ApplicationsMd Tanvir Arafin, Dhananjay Anand, Gang Qu. 161-166 [doi]
• A Novel Side-Channel Timing Attack on GPUsZhen Hang Jiang, Yunsi Fei, David R. Kaeli. 167-172 [doi]
• Cyclic Obfuscation for Creating SAT-Unresolvable CircuitsKaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin. 173-178 [doi]
• Double DIP: Re-Evaluating Security of Logic Encryption AlgorithmsYuanqi Shen, Hai Zhou. 179-184 [doi]
• Efficient Critical Path Selection Under a Probabilistic Delay ModelAhish Mysore Somashekar, Spyros Tragoudas. 185-190 [doi]
• Combining Restorability and Error Detection Ability for Effective Trace Signal SelectionBinod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh. 191-196 [doi]
• Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-FlopsYuwen Dave Lin, Charles H.-P. Wen, Herming Chiueh. 197-202 [doi]
• Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAsLuca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi. 203-208 [doi]
• Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing InterferenceNikolaos Zompakis, Michail Noltsis, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris. 209-214 [doi]
• Design Automation for Paper Microfluidics with Passive Flow SubstratesJoshua Potter, William H. Grover, Philip Brisk. 215-220 [doi]
• Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation ComputingMd. Amimul Ehsan, Zhen Zhou, Yang Yi 0002. 221-226 [doi]
• A Method for Phase Noise Analysis of RF CircuitsDimo Martev, Sven Hampel, Ulf Schlichtmann. 227-231 [doi]
• Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse EngineeringLeonid Azriel, Ran Ginosar, Avi Mendelson. 233-238 [doi]
• Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo TheoriesGhaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria. 239-244 [doi]
• Fine-Grain Program Snippets Generator for Mobile Core DesignShuang Song, Raj Desikan, Mohamad Barakat, Sridhar Sundaram, Andreas Gerstlauer, Lizy K. John. 245-250 [doi]
• Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen. 251-256 [doi]
• A Thermal-Balanced Variable-Sized-Bin-Packing Approach for Energy Efficient Multi-Core Real-Time SchedulingShi Sha, Wujie Wen, Shaolei Ren, Gang Quan. 257-262 [doi]
• Quantitative Modeling of Thermo-Optic Effects in Optical Networks-on-ChipWeichen Liu, Peng Wang, Mengquan Li, Yiyuan Xie, Nan Guan. 263-268 [doi]
• A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set TimeSamira Ataei, James E. Stine. 269-274 [doi]
• Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change MemoriesLei Jiang, Sparsh Mittal, Wujie Wen. 275-280 [doi]
• Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAMChaobing Zhou, Libo Huang, Zhisheng Li, Tan Zhang, Qiang Dou. 281-286 [doi]
• A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature GenerationPeng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei. 287-292 [doi]
• Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit AdditionLinbin Chen, Fabrizio Lombardi, Paolo Montuschi, Jie Han, Weiqiang Liu. 293-298 [doi]
• Advanced Low Power Spintronic Memories beyond STT-MRAMWang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao. 299-304 [doi]
• Exploiting Non-Volatility for Information ProcessingRobert Perricone, Li Tang, Michael T. Niemier, Xiaobo Sharon Hu. 305-310 [doi]
• Neuromorphic Computing based on Resistive RAMZixuan Chen, Huaqiang Wu, Bin Gao, Peng Yao, Xinyi Li, He Qian. 311-315 [doi]
• Implications of the Use of Magnetic Tunnel Junctions as Synapses in Neuromorphic SystemsAdrien F. Vincent, Nicolas Locatelli, Qifan Wu, Damien Querlioz. 317-320 [doi]
• Security Threats and Countermeasures in Three-Dimensional Integrated CircuitsJaya Dofe, Peng Gu, Dylan Stow, Qiaoyan Yu, Eren Kursun, Yuan Xie 0001. 321-326 [doi]
• Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated CircuitsJaya Dofe, Zhiming Zhang, Qiaoyan Yu, Chen Yan, Emre Salman. 327-332 [doi]
• The Need for Declarative Properties in Digital IC SecurityMohamed El Massad, Frank Imeson, Siddharth Garg, Mahesh Tripunitara. 333-338 [doi]
• Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-AuthenticationQihang Shi, Kan Xiao, Domenic Forte, Mark M. Tehranipoor. 339-344 [doi]
• An Empirical Study on Gate Camouflaging Methods Against Circuit Partition AttackXueyan Wang, Qiang Zhou, Yici Cai, Gang Qu. 345-350 [doi]
• What to Lock?: Functional and Parametric LockingMuhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran. 351-356 [doi]
• Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail?Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin. 357-362 [doi]
• Comparative Analysis of Hardware Obfuscation for IP ProtectionSarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, Swarup Bhunia. 363-368 [doi]
• Efficient and Secure On-Chip Reconfigurable Voltage Regulation for IoT DevicesSelçuk Köse. 369-374 [doi]
• Design Space Modeling and Simulation for Physically Constrained 3D CPUsCaleb Serafy, Zhiyuan Yang, Ankur Srivastava. 375-380 [doi]
• Automated Design of Stable Power Delivery Systems for Heterogeneous IoT SystemsInna Partin-Vaisband. 381-386 [doi]
• Work Load Scheduling For Multi Core Systems With Under-Provisioned Power DeliveryDivya Pathak, Houman Homayoun, Ioannis Savidis. 387-392 [doi]
• Bioinspired Programming of Resistive Memory Devices for Implementing Spiking Neural NetworksElisa Vianello, Thilo Werner, Alessandro Grossi, Etienne Nowak, Barbara De Salvo, Luca Perniola, Olivier Bichler, Blaise Yvert. 393-398 [doi]
• A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner PointsKuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin. 399-402 [doi]
• An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAsXiaodong Xu, Qi Xu, Jinglei Huang, Song Chen. 403-406 [doi]
• Communication-aware Partitioning for Energy Optimization of Large FPGA DesignsKalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan. 407-410 [doi]
• Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCsYong Chen, Emil Matús, Gerhard P. Fettweis. 411-414 [doi]
• Random Forest Architectures on FPGA for Multiple ApplicationsXiang Lin, R. D. Shawn Blanton, Donald E. Thomas. 415-418 [doi]
• Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCsWooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer, Lizy K. John. 419-422 [doi]
• An FPGA Coarse Grained Intermediate Fabric for Regular Expression SearchThomas Luinaud, Yvon Savaria, J. M. Pierre Langlois. 423-426 [doi]
• Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded SystemsHuimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang. 427-430 [doi]
• Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body BiasRajsaktish Sankaranarayanan, Matthew R. Guthaus. 431-434 [doi]
• Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative UnitXuncheng Zou, Bo Liu, Shigetoshi Nakatake. 435-438 [doi]
• Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data RateGyunam Jeon, Yong-Bin Kim. 439-442 [doi]
• An Energy Combiner Design for Multiple Microbial Energy Harvesting SourcesRidvan Umaz, Lei Wang 0003. 443-446 [doi]
• LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic BiochipsLingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai. 447-450 [doi]
• Throughput Optimization for Lifetime Budgeting in Many-Core SystemsLiang Wang, Xiaohang Wang, Ho-Fung Leung, Terrence S. T. Mak. 451-454 [doi]
• A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faultsSarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan. 455-458 [doi]
• Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam CarvingBrian Crites, Karen Kong, Philip Brisk. 459-462 [doi]
• ProACt: A Processor for High Performance On-demand Approximate ComputingArun Chandrasekharan, Daniel Große, Rolf Drechsler. 463-466 [doi]
• Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural NetworksZihao Yuan, Ji Li, Zhe Li, Caiwen Ding, Ao Ren, Bo Yuan, Qinru Qiu, Jeffrey Draper, Yanzhi Wang. 467-470 [doi]
• Computing Polynomials with Positive Coefficients using Stochastic Logic by Double-NAND ExpansionSayed Ahmad Salehi, Yin Liu, Marc D. Riedel, Keshab K. Parhi. 471-474 [doi]
• On the Role of Sequential Circuits in Stochastic ComputingPai-Shun Ting, John P. Hayes. 475-478 [doi]
• Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic SystemsSagarvarma Sayyaparaju, Gangotree Chakma, Sherif Amer, Garrett S. Rose. 479-482 [doi]
• Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register BankSean Kramer, Zhiming Zhang, Jaya Dofe, Qiaoyan Yu. 483-486 [doi]
• Using Security Invariant To Verify Confidentiality in Hardware DesignShuyu Kong, Yuanqi Shen, Hai Zhou. 487-490 [doi]
• Leveraging All-Spin Logic to Improve Hardware SecurityQutaiba Alasad, Jiann Yuan, Deliang Fan. 491-494 [doi]