Abstract is missing.
- Complementary IBS: Application specific error correction for PUFsMatthias Hiller, Dominik Merli, Frederic Stumpf, Georg Sigl. 1-6 [doi]
- Buskeeper PUFs, a promising alternative to D Flip-Flop PUFsPeter Simons, Erik van der Sluis, Vincent van der Leest. 7-12 [doi]
- Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistorsJing Ju, Jim Plusquellic, Raj Chakraborty, Reza M. Rad. 13-20 [doi]
- A novel method for watermarking sequential circuitsMatthew Lewandowski, Richard Meana, Matthew Morrison, Srinivas Katkoori. 21-24 [doi]
- Reliability enhancement of bi-stable PUFs in 65nm bulk CMOSMudit Bhargava, Cagla Cakir, Ken Mai. 25-30 [doi]
- SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuitsLakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak, Ranga Vemuri. 31-36 [doi]
- Register leakage masking using Gray codeHoussem Maghrebi, Sylvain Guilley, Emmanuel Prouff, Jean-Luc Danger. 37-42 [doi]
- An adaptable, modular, and autonomous side-channel vulnerability evaluatorMichael Zohner, Marc Stöttinger, Sorin A. Huss, Oliver Stein. 43-48 [doi]
- Evaluating security requirements in a general-purpose processor by combining assertion checkers with code coverageMichael Bilzor, Ted Huffmire, Cynthia E. Irvine, Timothy E. Levin. 49-54 [doi]
- HTOutlier: Hardware Trojan detection with side-channel signature outlier identificationJie Zhang, Haile Yu, Qiang Xu. 55-58 [doi]
- FPGA based trustworthy authentication technique using Physically Unclonable Functions and artificial intelligenceSwetha Pappala, Mohammed Y. Niamat, Weiqing Sun. 59-62 [doi]
- t-Private logic synthesis on FPGAsJungmin Park, Akhilesh Tyagi. 63-68 [doi]
- Interacting with Hardware Trojans over a networkMohammed M. Farag, Lee W. Lerner, Cameron D. Patterson. 69-74 [doi]
- Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structureCharles Lamech, Jim Plusquellic. 75-82 [doi]
- Reverse engineering circuits using behavioral pattern miningWenchao Li, Zach Wasson, Sanjit A. Seshia. 83-88 [doi]
- Glitch-free implementation of masking in modern FPGAsAmir Moradi, Oliver Mischke. 89-95 [doi]
- A systematic M safe-error detection in hardware implementations of cryptographic algorithmsDusko Karaklajic, Junfeng Fan, Ingrid Verbauwhede. 96-101 [doi]
- Functional integrated circuit analysisDmitry Nedospasov, Jean-Pierre Seifert, Alexander Schlösser, Susanna Orlic. 102-107 [doi]
- Performance metrics and empirical results of a PUF cryptographic key generation ASICMeng-Day (Mandel) Yu, Richard Sowell, Alok Singh 0003, David M'Raïhi, Srinivas Devadas. 108-115 [doi]
- HSDL: A Security Development Lifecycle for hardware technologiesHareesh Khattri, Kumar V. Mangipudi, Salvador Mandujano. 116-121 [doi]
- Design solutions for securing SRAM cell against power analysisVladimir Rozic, Wim Dehaene, Ingrid Verbauwhede. 122-127 [doi]
- On charge sensors for FIB attack detectionClemens Helfmeier, Christian Boit, Uwe Kerst. 128-133 [doi]
- Detection of probing attempts in secure ICsSalvador Manich, Markus S. Wamser, Georg Sigl. 134-139 [doi]
- Fault Round Modification Analysis of the advanced encryption standardJean-Max Dutertre, Amir-Pasha Mirbaha, David Naccache, Anne-Lise Ribotta, Assia Tria, Thierry Vaschalde. 140-145 [doi]
- Improved algebraic side-channel attack on AESMohamed Saied Emam Mohamed, Stanislav Bulygin, Michael Zohner, Annelie Heuser, Michael Walter, Johannes Buchmann. 146-151 [doi]