Abstract is missing.
- Defensive dropout for hardening deep neural networks under adversarial attacksSiyue Wang, Xiao Wang, Pu Zhao, Wujie Wen, David Kaeli, Peter Chin, Xue Lin. [doi]
- A fast thermal-aware fixed-outline floorplanning methodology based on analytical modelsJai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. [doi]
- AXNet: approximate computing using an end-to-end trainable neural networkZhenghao Peng, Xuyang Chen, Chengwen Xu, Naifeng Jing, Xiaoyao Liang, Cewu Lu, Li Jiang 0002. [doi]
- Analytical solution of Poisson's equation and its application to VLSI global placementWenxing Zhu, Zhipeng Huang 0009, Jianli Chen, Yao-Wen Chang. 2 [doi]
- Novel proximal group ADMM for placement considering fogging and proximity effectsJianli Chen, Li Yang, Zheng Peng 0002, Wenxing Zhu, Yao-Wen Chang. 3 [doi]
- Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systemsShih-Chun Chen, Richard Sun, Yao-Wen Chang. 4 [doi]
- IC/IP piracy assessment of reversible logicSamah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu 0001, Ramesh Karri. 5 [doi]
- TimingSAT: timing profile embedded SAT attackAbhishek Chakraborty 0001, Yuntao Liu, Ankur Srivastava. 6 [doi]
- Towards provably-secure analog and mixed-signal locking against overproductionNithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran. 7 [doi]
- Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICsSatwik Patnaik, Mohammed Ashraf, Ozgur Sinanoglu, Johann Knechtel. 8 [doi]
- Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-baseSebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid. 9 [doi]
- NID: processing binary convolutional neural network in commodity DRAMJaehyeong Sim, Hoseok Seol, Lee-Sup Kim. 10 [doi]
- Scalable-effort ConvNets for multilevel classificationValentino Peluso, Andrea Calimera. 12 [doi]
- Emerging reconfigurable nanotechnologies: can they support future electronics?Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar 0001. 13 [doi]
- Design and algorithm for clock gating and flip-flop co-optimizationGiyoung Yang, Taewhan Kim. 14 [doi]
- Macro-aware row-style power delivery network design for better routabilityJai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen. 15 [doi]
- Modeling and optimization of magnetic core TSV-inductor for on-chip DC-DC converterBaixin Chen, Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi. 16 [doi]
- Machine-learning-based dynamic IR drop prediction for ECOYen-Chun Fang, Heng-Yi Lin, Min-Yan Su, Chien-Mo James Li, Eric Jia-Wei Fang. 17 [doi]
- Privacy-preserving deep learning and inferenceM. Sadegh Riazi, Farinaz Koushanfar. 18 [doi]
- Machine learning IP protectionRosario Cammarota, Indranil Banerjee, Ofer Rosenberg. 19 [doi]
- Assured deep learning: practical defense against adversarial attacksBita Darvish Rouhani, Mohammad Samragh, Mojan Javaheripi, Tara Javidi, Farinaz Koushanfar. 20 [doi]
- Tetris: re-architecting convolutional neural network computation for machine learning acceleratorsHang Lu, Xin Wei, Ning Lin, Guihai Yan, Xiaowei Li. 21 [doi]
- FCN-engine: accelerating deconvolutional layers in classic CNN processorsDawen Xu, Kaijie Tu, Ying Wang, Cheng Liu, Bingsheng He, Huawei Li. 22 [doi]
- Designing adaptive neural networks for energy-constrained image classificationDimitrios Stamoulis, Ting-Wu Rudy Chin, Anand Krishnan Prakash, Haocheng Fang, Sribhuvan Sajja, Mitchell Bognar, Diana Marculescu. 23 [doi]
- FATE: fast and accurate timing error prediction framework for low power DNN accelerator designJeff Jun Zhang, Siddharth Garg. 24 [doi]
- Waterfall is too slow, let's go Agile: multi-domain coupling for synthesizing automotive cyber-physical systemsDebayan Roy, Michael Balszun, Thomas Heurung, Samarjit Chakraborty, Amol Naik. 25 [doi]
- Model-based and data-driven approaches for building automation and controlTianshu Wei, Xiaoming Chen, Xin Li, Qi Zhu. 26 [doi]
- Design automation for battery systemsSwaminathan Narayanaswamy, Sangyoung Park, Sebastian Steinhorst, Samarjit Chakraborty. 27 [doi]
- RFUZZ: coverage-directed fuzz testing of RTL on FPGAsKevin Laeufer, Jack Koenig, Donggyu Kim, Jonathan Bachrach, Koushik Sen. 28 [doi]
- Steep coverage-ascent directed test generation for shared-memory verification of multicore chipsGabriel A. G. Andrade, Marleson Graf, Nícolas Pfeifer, Luiz C. V. dos Santos. 29 [doi]
- SMTSampler: efficient stimulus generation from complex SMT constraintsRafael Dutra, Jonathan Bachrach, Koushik Sen. 30 [doi]
- DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learningMeng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang. 31 [doi]
- A ferroelectric FET based power-efficient architecture for data-intensive computingYun Long, Taesik Na, Prakshi Rastogi, Karthik Rao, Asif Islam Khan, Sudhakar Yalamanchili, Saibal Mukhopadhyay. 32 [doi]
- EMAT: an efficient multi-task architecture for transfer learning using ReRAMFan Chen, Hai Li. 33 [doi]
- Co-manage power delivery and consumption for manycore systems using reinforcement learningHaoran Li, Zhongyuan Tian, Rafael K. V. Maeda, Xuanqi Chen, Jun Feng, Jiang Xu 0001. 34 [doi]
- Adaptive-precision framework for SGD using deep Q-learningWentai Zhang, Hanxian Huang, Jiaxi Zhang, Ming Jiang 0001, Guojie Luo. 35 [doi]
- Differentiated handling of physical scenes and virtual objects for mobile augmented realityChih-Hsuan Yen, Wei-Ming Chen, Pi-Cheng Hsiu, Tei-Wei Kuo. 36 [doi]
- DATC RDF: an academic flow from logic synthesis to detailed routingJinwook Jung, Iris Hui-Ru Jiang, Jianli Chen, Shih-Ting Lin, Yih-Lang Li, Victor N. Kravets, Gi-Joon Nam. 37 [doi]
- Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variationsXin Fan, Rui Wang, Tobias Gemmeke. 38 [doi]
- Comparing voltage adaptation performance between replica and in-situ timing monitorsYutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto. 39 [doi]
- Strain-aware performance evaluation and correction for OTFT-based flexible displaysTengtao Li, Sachin S. Sapatnekar. 40 [doi]
- Achieving fast sanitization with zero live data copy for MLC flash memoryPing-Hsien Lin, Yu-Ming Chang, Yung-Chun Li, Wei-Chen Wang, Chien-Chung Ho, Yuan-Hao Chang. 41 [doi]
- Architecting data placement in SSDs for efficient secure deletion implementationHoda Aghaei Khouzani, Chen Liu, Chengmo Yang. 42 [doi]
- AxBA: an approximate bus architecture frameworkJacob R. Stevens, Ashish Ranjan, Anand Raghunathan. 43 [doi]
- Security: the dark side of approximate computing?Francesco Regazzoni, Cesare Alippi, Ilia Polian. 44 [doi]
- Security aspects of neuromorphic MPSoCsJohanna Sepúlveda, Cezar Reinbrecht, Jean-Philippe Diguet. 45 [doi]
- Vulnerability-tolerant secure architecturesTodd M. Austin, Valeria Bertacco, Baris Kasikci, Sharad Malik, Mohit Tiwari. 46 [doi]
- Machine learning for performance and power modeling of heterogeneous systemsJoseph L. Greathouse, Gabriel H. Loh. 47 [doi]
- Machine learning for design space exploration and optimization of manycore systemsRyan Gary Kim, Janardhan Rao Doppa, Partha Pratim Pande. 48 [doi]
- Failure prediction based on anomaly detection for complex core routersShi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 49 [doi]
- Invocation-driven neural approximate computing with a multiclass-classifier and multiple approximatorsHaiyue Song, Chengwen Xu, Qiang Xu 0001, Zhuoran Song, Naifeng Jing, Xiaoyao Liang, Li Jiang 0002. 50 [doi]
- Deterministic methods for stochastic computing using low-discrepancy sequencesM. Hassan Najafi, David J. Lilja, Marc D. Riedel. 51 [doi]
- Design space exploration of multi-output logic function approximationsJorge Echavarria, Stefan Wildermann, Jürgen Teich. 52 [doi]
- 3DICT: a reliable and QoS capable mobile process-in-memory architecture for lookup-based CNNs in 3D XPoint ReRAMsQian Lou, Wujie Wen, Lei Jiang 0001. 53 [doi]
- Aliens: a novel hybrid architecture for resistive random-access memoryBing Wu, Dan Feng 0001, Wei Tong, Jingning Liu, Shuai Li, Mingshun Yang, Chengning Wang, Yang Zhang. 54 [doi]
- FELIX: fast and energy-efficient logic in memorySaransh Gupta, Mohsen Imani, Tajana Rosing. 55 [doi]
- DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAsXiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen. 56 [doi]
- Algorithm-hardware co-design of single shot detector for fast object detection on FPGAsYufei Ma, Tu Zheng, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo. 57 [doi]
- TGPA: tile-grained pipeline architecture for low latency CNN inferenceXuechao Wei, Yun Liang 0001, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong. 58 [doi]
- Customized locking of IP blocks on a multi-million-gate SoCAbhrajit Sengupta, Mohammed Thari Nabeel, Mohammed Ashraf, Ozgur Sinanoglu. 59 [doi]
- Dynamic resource management for heterogeneous many-coresJörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch. 60 [doi]
- Online learning for adaptive optimization of heterogeneous SoCsGanapati Bhat, Sumit K. Mandal, Ujjwal Gupta, Ümit Y. Ogras. 61 [doi]
- Hybrid on-chip communication architectures for heterogeneous manycore systemsBiresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, Radu Marculescu. 62 [doi]
- A practical detailed placement algorithm under multi-cell spacing constraintsYu-Hsiang Cheng, Ding-Wei Huang, Wai-Kei Mak, Ting-Chi Wang. 63 [doi]
- Mixed-cell-height placement considering drain-to-drain abutmentYu-Wei Tseng, Yao-Wen Chang. 64 [doi]
- Mixed-cell-height legalization considering technology and region constraintsZiran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang. 65 [doi]
- Mixed-cell-height placement with complex minimum-implant-area constraintsJianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang. 66 [doi]
- RAPID: read acceleration for improved performance and endurance in MLC/TLC NVMsPoovaiah M. Palangappa, Kartik Mohanram. 67 [doi]
- Sneak path free reconfiguration of via-switch crossbars based FPGARyutaro Doi, Jaehoon Yu, Masanori Hashimoto. 68 [doi]
- Mixed size crossbar based RRAM CNN accelerator with overlapped mapping methodZhenhua Zhu, Jilan Lin, Ming Cheng, Lixue Xia, Hanbo Sun, Xiaoming Chen, Yu Wang, Huazhong Yang. 69 [doi]
- Enhancing the solution quality of hardware ising-model solver via parallel temperingHidenori Gyoten, Masayuki Hiromoto, Takashi Sato. 70 [doi]
- Online human activity recognition using low-power wearable devicesGanapati Bhat, Ranadeep Deb, Vatika Vardhan Chaurasia, Holly Shill, Ümit Y. Ogras. 72 [doi]
- Shadow attacks on MEDA biochipsMohammed Shayan, Sukanta Bhattacharjee, Tung-Che Liang, Jack Tang, Krishnendu Chakrabarty, Ramesh Karri. 73 [doi]
- LeapChain: efficient blockchain verification for embedded IoTEmanuel Regnath, Sebastian Steinhorst. 74 [doi]
- Robust object estimation using generative-discriminative inference for secure robotics applicationsYanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins. 75 [doi]
- Efficient utilization of adversarial training towards robust machine learners and its analysisSai Manoj P. D., Sairaj Amberkar, Setareh Rafatirad, Houman Homayoun. 78 [doi]
- Majority logic synthesisLuca Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken. 79 [doi]
- RouteNet: routability prediction for mixed-size designs using convolutional neural networkZhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Nvidia Corporation. 80 [doi]
- TritonRoute: an initial detailed router for advanced VLSI technologiesAndrew B. Kahng, Lutong Wang, Bangqi Xu. 81 [doi]
- A multithreaded initial detailed routing algorithm considering global routing guidesFan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu, Yao-Wen Chang. 82 [doi]
- Extending ML-OARSMT to net open locator with efficient and effective boolean operationsBing-Hui Jiang, Hung-Ming Chen. 83 [doi]
- Logic synthesis of binarized neural networks for efficient circuit implementationChia-Chih Chi, Jie-Hong R. Jiang. 84 [doi]
- Canonicalization of threshold logic representation and its applicationsSiang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang. 85 [doi]
- DALS: delay-driven approximate logic synthesisZhuangzhuang Zhou, Yue Yao, Shuyang Huang, Sanbao Su, Chang Meng, Weikang Qian. 86 [doi]
- Unlocking fine-grain parallelism for AIG rewritingVinicius Neves Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis. 87 [doi]
- High-level synthesis with timing-sensitive information flow enforcementZhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang. 88 [doi]
- Property specific information flow analysis for hardware security verificationWei Hu, Armaiti Ardeshiricham, Mustafa S. Gobulukoglu, Xinmu Wang, Ryan Kastner. 89 [doi]
- HISA: hardware isolation-based secure architecture for CPU-FPGA embedded systemsMengmei Ye, Xianglong Feng, Sheng Wei 0001. 90 [doi]
- SWAN: mitigating hardware trojans with design ambiguityTimothy Linscott, Pete Ehrett, Valeria Bertacco, Todd M. Austin. 91 [doi]
- Security for safety: a path toward building trusted autonomous vehiclesRaj Gautam Dutta, Feng Yu, Teng Zhang, Yaodan Hu, Yier Jin. 92 [doi]
- Hardware-accelerated data acquisition and authentication for high-speed video streams on future heterogeneous automotive processing platformsMartin Geier, Fabian Franzen, Samarjit Chakraborty. 93 [doi]
- Network and system level security in connected vehicle applicationsHengyi Liang, Matthew Jagielski, Bowen Zheng, Chung-Wei Lin, Eunsuk Kang, Shinichi Shiraishi, Cristina Nita-Rotaru, Qi Zhu 0002. 94 [doi]
- A safety and security architecture for reducing accidents in intelligent transportation systemsQian Chen, Azizeh Khaled Sowan, Shouhuai Xu. 95 [doi]
- The need and opportunities of electromigration-aware integrated circuit designSteve Bigalke, Jens Lienig, Göran Jerke, Jürgen Scheible, Roland Jancke. 96 [doi]
- Uncertainty quantification of electronic and photonic ICs with non-Gaussian correlated process variationsChunfeng Cui, Zheng Zhang. 97 [doi]
- Parallelizable Bayesian optimization for analog and mixed-signal rare failure detection with high coverageHanbin Hu, Peng Li, Jianhua Z. Huang. 98 [doi]
- Transient circuit simulation for differential algebraic systems using matrix exponentialPengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang. 99 [doi]
- CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCsMengchu Li, Tsun-Ming Tseng, Davide Bertozzi, Mahdi Tala, Ulf Schlichtmann. 100 [doi]
- A cross-layer methodology for design and optimization of networks in 2.5D systemsAyse Kivilcim Coskun, Furkan Eris, Ajay Joshi, Andrew B. Kahng, Yenai Ma, Vaishnav Srinivas. 101 [doi]
- Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree searchYong Hu, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 102 [doi]
- HLS-based optimization and design space exploration for applications with variable loop boundsYoung Kyu Choi, Jason Cong. 103 [doi]
- HLSPredict: cross platform performance prediction for FPGA high-level synthesisKenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk. 104 [doi]
- C-GOOD: C-code generation framework for optimized on-device deep learningDuseok Kang, Euiseok Kim, Inpyo Bae, Bernhard Egger, Soonhoi Ha. 105 [doi]
- LiteHAX: lightweight hardware-assisted attestation of program executionGhada Dessouky, Tigist Abera, Ahmad Ibrahim 0002, Ahmad-Reza Sadeghi. 106 [doi]
- SCADET: a side-channel attack detection tool for tracking prime+probeMajid Sabbagh, Yunsi Fei, Thomas Wahl, A. Adam Ding. 107 [doi]
- Industrial experiences with resource management under software randomization in ARINC653 avionics environmentsLeonidas Kosmidis, Cristian Maxim, Victor Jégu, Francis Vatrinet, Francisco J. Cazorla. 108 [doi]
- Single flux quantum circuit technology and CAD overviewCoenrad Fourie. 109 [doi]
- Design automation methodology and tools for superconductive electronicsMassoud Pedram, Yanzhi Wang. 110 [doi]
- Multi-terminal routing with length-matching for rapid single flux quantum circuitsPei-Yi Cheng, Kazuyoshi Takagi, Tsung-Yi Ho. 111 [doi]
- Electromagnetic equalizer: an active countermeasure against EM side-channel attackChenguang Wang, Yici Cai, Haoyi Wang, Qiang Zhou 0001. 112 [doi]
- GPU acceleration of RSA is vulnerable to side-channel timing attacksChao Luo, Yunsi Fei, David R. Kaeli. 113 [doi]
- Remote inter-chip power analysis side-channel attacks at board-levelFalk Schellenberg, Dennis R. E. Gnad, Amir Moradi 0001, Mehdi Baradaran Tahoori. 114 [doi]
- Effective simple-power analysis attacks of elliptic curve cryptography on embedded systemsChao Luo, Yunsi Fei, David R. Kaeli. 115 [doi]
- SODA: stencil with optimized dataflow architectureYuze Chi, Jason Cong, Peng Wei, Peipei Zhou. 116 [doi]
- PolySA: polyhedral-based systolic array auto-compilationJason Cong, Jie Wang. 117 [doi]
- An efficient data reuse strategy for multi-pattern data accessWensong Li, Fan Yang 0001, Hengliang Zhu, Xuan Zeng 0001, Dian Zhou. 118 [doi]
- Optimizing data layout and system configuration on FPGA-based heterogeneous platformsHou-Jen Ko, Zhiyuan Li, Samuel P. Midkiff. 119 [doi]
- Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusionKofi Otseidu, Tianyu Jia, Joshua Bryne, Levi Hargrove, Jie Gu. 120 [doi]
- Area-efficient and low-power face-to-face-bonded 3D liquid state machine designBon Woong Ku, Yu Liu, Yingyezhe Jin, Peng Li, Sung Kyu Lim. 121 [doi]
- DIMA: a depthwise CNN in-memory acceleratorShaahin Angizi, Zhezhi He, Deliang Fan. 122 [doi]
- Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochipsYing Zhu, Bing Li 0005, Tsung-Yi Ho, Qin Wang 0005, Hailong Yao, Robert Wille, Ulf Schlichtmann. 123 [doi]
- Multi-physics-based FEM analysis for post-voiding analysis of electromigration failure effectsHengyang Zhao, Sheldon X.-D. Tan. 124 [doi]
- Estimating and optimizing BTI aging effects: from physics to CADHussam Amrouch, Victor M. van Santen, Jörg Henkel. 125 [doi]
- 2: process, voltage, temperature and time-dependent variability in scaled CMOS processA. K. M. Mahfuzul Islam, Hidetoshi Onodera. 126 [doi]
- Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-MLDaniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann. 127 [doi]
- Computer-aided design for quantum computationRobert Wille, Austin G. Fowler, Yehuda Naveh. 128 [doi]
- PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliersAlireza Mahzoon, Daniel Große, Rolf Drechsler. 129 [doi]
- A formal instruction-level GPU model for scalable verificationYue Xing, Bo-Yuan Huang, Aarti Gupta, Sharad Malik. 130 [doi]
- Fast FPGA emulation of analog dynamics in digitally-driven systemsSteven Herbst, ByongChan Lim, Mark Horowitz. 131 [doi]
- SPN dash: fast detection of adversarial attacks on mobile via sensor pattern noise fingerprintingKent W. Nixon, Jiachen Mao, Juncheng Shen, Huanrui Yang, Hai (Helen) Li, Yiran Chen. 132 [doi]
- Watermarking deep neural networks for embedded systemsJia Guo, Miodrag Potkonjak. 133 [doi]
- DeepFense: online accelerated defense against adversarial deep learningBita Darvish Rouhani, Mohammad Samragh, Mojan Javaheripi, Tara Javidi, Farinaz Koushanfar. 134 [doi]
- Enabling deep learning at the IoT edgeLiangzhen Lai, Naveen Suda. 135 [doi]
- Searching toward pareto-optimal device-aware neural architecturesAn-Chieh Cheng, Jin-Dong Dong, Chi-Hung Hsu, Shu-Huan Chang, Min Sun, Shih-Chieh Chang, Jia-Yu Pan, Yu-Ting Chen, Wei Wei, Da-Cheng Juan. 136 [doi]
- Hardware-aware machine learning: modeling and optimizationDiana Marculescu, Dimitrios Stamoulis, Ermao Cai. 137 [doi]