Table of Contents

• An Interference Analysis of Interconnection NetworksLaxmi N. Bhuyan, C. W. Lee. 2-9
• Generalized Delta NetworksManoj Kumar, J. Robert Jump. 10-18
• Expanding and Contracting SW-Banyan NetworksDoug DeGroot. 19-24
• A Comparison of Circuit Switching and Packet Switching for Data Transfer in Two Simple Image processing AlgorithmsMehrad Yasrebi, Sanjay R. Deshpande, James C. Browne. 25-28
• Numerical Experiments with the Massively parallel ProcessorEfstratios Gallopoulos, S. D. McEwan. 29-35
• An M-Step preconditioned Conjugate Gradient Method for Parallel ComputationLoyce M. Adams. 36-43
• Minimizing Inner Product Data Dependencies in Conjugate Gradient IterationJohn Van Rosendale. 44-46
• New Matrix Equation Solvers in GF(2) Employing Cramer with Chio MethodYoshiyasu Takefuji, Takakazu Kurokawa, Masato Ishizaki, Hideo Aiso. 47-50
• Specification and Implementation of an Integrated Packet Communication Facility for an Array ComputerBharat Deep Rathi, Sanjay R. Deshpande, Matthew Sejnowski, Don Walker, Roy M. Jenevein, G. Jack Lipovski, James C. Browne. 51-58
• Timing Control of VLSI Based NlogN and Crossbar NetworksSanjay Dhar, Mark A. Franklin, Donald F. Wann. 59-64
• Easily-Testable (N, K) Shuffle/Exchange NetworksDavid C. H. Lee, John Paul Shen. 65-70
• Fault Tolerance Schemes in Shuffle-Exchange Type Interconnection NetworksKrishnan Padmanabhan, Duncan H. Lawrie. 71-75
• A Condition Known to be Sufficient for Rearrangeability of the Benes Class of Interconnection Networks with 2x2 Switches Is Also NecessarySuresh C. Kothari, S. Lakshmivarahan. 76-78
• A Fast Algorithm for Concurrent LU Decomposition and Matrix InversionMing-Yang Chern, Tadao Murata. 79-86
• Vector Computer for Sparse Matrix OperationsQing Shi Gao, Rong-Quan Wang. 87-89
• Efficient Matrix Multiplications on a Concurrent Data-Loading Array ProcessorMing-Yang Chern, Tadao Murata. 90-94
• Highly Parallel Processor Array PAX for Wide Scientific ApplicationsTsutomu Hoshino, Tomonori Shirakawa, Takeshi Kamimura, Takahisa Kageyama, Kiyo Takenouchi, Hidehiko Abe, Satoshi Sekiguchi, Yoshio Oyanagi, Toshio Kawai. 95-105
• Partitioning Job Structures for SW-Banyan NetworksDoug DeGroot. 106-113
• Configuring Computation Tree Topologies on a Distributed Computing SystemWoei Lin, Chuan-lin Wu. 114-116
• Performing the Shuffle with the PM2I and Illiac SIMD Interconnection NetworksRobert R. Seban, Howard Jay Siegel. 117-125
• A Classification of Cube-Connected Networks with a Simple Control SchemeA. Yavuz Oruç. 126-131
• The FEM-2 Design MethodTerrence W. Pratt, Loyce M. Adams, Piyush Mehrotra, John Van Rosendale, Robert G. Voigt, Merrell L. Patrick. 132-134
• A Multi-Microprocessor System for Concurrent LISPShigeo Sugimoto, Kiyoshi Agusa, Koichi Tabata, Yutaka Ohno. 135-143
• A Multi-Micro System for I/O Intensive ApplicationsF. M. Tse. 144-147
• Pipeline and Parallel Architectures for Computer Communication SystemsArumalla V. Reddi. 148-150
• An Interface Message Processor with a Multiprocessing ArchitectureKrish Purswani, Bijan Jabbari. 151-153
• A Class of Graphs for Processor InterconnectionJon G. Kuhl, Sudhakar M. Reddy, P. Raghavan. 154-157
• Dense Bus Connection NetworksKarl W. Doty. 158-160
• A Simulation Study of Multimicrocomputer NetworksDaniel A. Reed. 161-163
• Evaluation of Multiprocessor Interconnect Structures with the Cm TestbedAndrew Wilson, Daniel P. Siewiorek, Zary Segall. 164-171
• Slot-Based Multi-Access Protocol for Local Computer NetworkA. I. Noor, G. S. Hope, O. P. Malik. 172-174
• New Connectivity and MSF Algorithms for Ultracomputer and PRAMBaruch Awerbuch, Tripurari Singh. 175-179
• Bridge-Connectivity and Biconnectivity Algorithms for Parallel Computer ModelsYung H. Tsin. 180-182
• Anomalies in Parallel Branch-and-Bound AlgorithmsTen-Hwang Lai, Sartaj Sahni. 183-190
• Experience with Two Parallel Programs Solving the Traveling Salesman ProblemJoseph Mohan. 191-193
• DOT, A Distributed Operating System Model of a Tree-Structured MultiprocessorScott Danforth. 194-201
• The Tree Machine: An Evaluation of Strategies for Reducing Program Loading TimePeyyun Peggy Li, S. Lennart Johnsson. 202-205
• Optimal Routing Algorithms in Multicomputer Networks Organized as Reconfigurable Binary TreesSvetlana P. Kartashev, Steven I. Kartashev. 206-213
• Sorting, Merging, Selecting, and Filtering on Tree and Pyramid MachinesQuentin F. Stout. 214-221
• Omni-sort: A Versatile Data Processing Operation for VLSIChing C. Hsiao, Lawrence Snyder. 222-225
• Pseudo Associative Linking: A High-Speed Searching Algorithm for Parallel ProcessorsF. P. Hiner III. 226-231
• Implementation of an Array and Vector Processing LanguageRonald H. Perrott, Danny Crookes, Peter Milligan, W. R. Martin Purdy. 232-239
• : A Parallel P-Code for Parallel Pascal and Other High Level LanguagesAnthony P. Reeves, John D. Bruner. 240-243
• The DC1 Flow Schema with the Data/Control-Driven EvaluationNam Sung Woo, Ashok K. Agrawala. 244-251
• Top-Down Data Flow ProgrammingYury Litvin. 252-254
• A Pipeline Machine for Image Processing ApplicationsIkram E. Abdou. 255-257
• An Evaluation Study of Six Topologies of Parallel Computer Architectures for Scene MatchingYee-Hong Yang, Tsung-Wei Sze. 258-260
• An Architecture for Efficient Generation of Fractal SurfacesStephen L. Stepoway, David L. Wells, Gerald R. Kane. 261-268
• An Architecture for the Real-Time Display and Manipulation of Three-Dimensional ObjectsSamuel M. Goldwasser, R. A. Reynolds. 269-274
• A Parallel Architecture for Labeling, Segmentation, and Lexical Processing in Speech UnderstandingEdward C. Bronson, Leah H. Jamieson. 275-280
• On the Algebraic Specification of Concurrency and CommunicationJean-Pierre Finance, M. S. Ouerghi. 281-288
• Introduction to the Poker Parallel Programming EnvironmentLawrence Snyder. 289-292
• A High Level Analysis Tool for Concurrent ProgramsPaolo Mancarella, Franco Turini. 293-302
• A Stream Definition for Von Neumann MultiprocessorsStephen J. Allan, R. R. Oldehoeft. 303-306
• A Database Machine for Very Large Relational DatabasesGhassan Z. Qadah, Keki B. Irani. 307-314
• Efficient Computing of Relational Join Operations by Means of Specialized HardwareYang-Chang Hong. 315-318
• A VLSI Modular Architecture Methodology for Realtime Signal Processing ApplicationsHungwen Li. 319-324
• EMSY85 : The Erlangen Multi-Processor System for a Broad Spectrum of ApplicationsGerhard Fritsch, W. Kleinoeder, Claus-Uwe Linster, Jens Volkert. 325-330
• Maximum Pipelining of Array Operations on Static Data Flow MachineJack B. Dennis, Guang R. Gao. 331-334
• A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow ApproachIsrael Koren, Gabriel M. Silberman. 335-337
• An Algorithm for Processor Allocation in a Dataflow Multiprocessing EnvironmentLawrence Y. Ho, Keki B. Irani. 338-340
• A Small, High-Speed Dataflow ProcessorWilliam Leler. 341-343
• Programmable Modular Signal Processor : A Data Flow Computer System for Real-Time Signal ProcessingPrashant S. Sawkar, Timothy J. Forquer, Richard P. Perry. 344-349
• A Simulation for MIMD Performance Prediction : Application to the S-1 MkIIa MultiprocessorTimothy S. Axelrod, Paul F. Dubois, Peter G. Eltgroth. 350-358
• Vectorization of Discrete Event SimulationAvinash Chandak, James C. Browne. 359-361
• Analysis of Backward Error Recovery for Concurrent Processes with Recovery BlocksKang G. Shin, Yann-Hang Lee. 362-366
• Improved Multiprocessor Garbage Collection AlgorithmsIan A. Newman, R. P. Stallard, M. C. Woodward. 367-368
• Efficiency of Feature Dependent Algorithms for the Parallel Processing of ImagesTrevor N. Mudge, Abdel-Rahman H. Tawil. 369-373
• Matching Parallel Algorithm and ArchitectureYetung P. Chiang, King-sun Fu. 374-380
• Coherent Flow of Information in Parallel SystemsBruce P. Lester. 381-383
• Virtual TimeDavid Jefferson. 384-394
• Process Management Overhead in a Speedup-Oriented MIMD SystemRuknet Cezzar, David Klappholz. 395-403
• Assigning Processes to Processors in Distributed SystemsElizabeth Williams. 404-406
• Preloading Schemes for the PASM Parallel Memory SystemDavid Lee Tuomenoksa, Howard Jay Siegel. 407-415
• Constructing a Parallel Implementation from High-Level Specifications: A Case Study Using Resource ExpressionsBharadwaj Jayaraman. 416-420
• Queueing Network Models for Parallel Processing of Task SystemsAlexander Thomasian, Paul F. Bay. 421-428
• On the Performance of Interleaved Memories with Non-Uniform Access ProbabilitiesHung-Chang Du, Jean-Loup Baer. 429-436
• A Markovian Queueing Network Model for Performance Evaluation of Bus-Deficient Multiprocessor SystemsIbrahim H. Önyüksel, Keki B. Irani. 437-439
• On Mapping Homogeneous Graphs on a Linear Array-Processor ModelI. V. Ramakrishnan, Donald S. Fussell, Abraham Silberschatz. 440-447
• Unifying VLSI Array Designs with Geometric TransformationsPeter R. Cappello, Kenneth Steiglitz. 448-457
• Design of Robust Systolic AlgorithmsPeter J. Varman, Donald S. Fussell. 458-460
• Structured Memory Access ArchitectureAndrew R. Pleszkun, Edward S. Davidson. 461-471
• A Simple Architecture for Low Level ParallelismCharles E. McDowell. 472-477
• Hierarchical Micro-Architectures of a Two-Level Microprogrammed Multiprocessor ComputerTakanobu Baba, Katsuhiro Yamazaki, Nobuyuki Hashimoto, Hiroyuki Kanai, Kenzo Okuda, Kazuhiko Hashimoto. 478-485
• Alternative Data Structures for Lists in Associative DevicesJ. L. Potter. 486-491
• Determination of the Rotational and Translational Components of a Flow Field Using a Content Addressable Parallel ProcessorMartha E. Steenstrup, Daryl T. Lawton, Charles C. Weems. 492-495
• Dynamic Relibility Modeling and Analysis of Computer NetworksSrinivas V. Makam, Cauligi S. Raghavendra. 496-502
• Functional Specification of Distributed SystemsGruia-Catalin Roman, Robert K. Israel. 503-505
• MOPAC: A Partitionable and Reconfigurable Multicomputer ArrayWong-Hua Lee, Miroslaw Malek. 506-510
• The Multiprocessor EMPRESS: A Useful Tool for Studying Parallelization ConceptsHans-Joerg Brundiers, Richard E. Buehrer, Hansmartin Friess, Milan Tadian. 511-513
• Performance of a Modular Interactive Data Analysis System (MIDAS)Creve Maples, Daniel Weaver, Douglas Logan, William Rathbun. 514-519
• The Homogeneous Multiprocessor Architecture : Structure and Performance AnalysisNikitas J. Dimopoulos. 520-523
• Cedar : A Large Scale MultiprocessorDaniel Gajski, David J. Kuck, Duncan H. Lawrie, Ahmed H. Sameh. 524-529
• Vector Optimization on the CYBER 205Clifford N. Arnold. 530-536
• Pipelined Evaluation of First-Order Recurrence SystemsLionel M. Ni, Kai Hwang. 537-543
• The Solution of Linear Recurrence Relations on Pipelined ProcessorsWilfried Oed, Otto Lange. 544-546
• Data-Stationary Instructions as a Way to Minimize Long Distance Communications in VLSIJohn Robert Burger. 547-553