Abstract is missing.
- Design or manufacturing: which will be best for the future of the semiconductor roadmap?Antun Domic. 1 [doi]
- RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithmDavid A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov. 2-9 [doi]
- Robust gate sizing via mean excess delay minimizationJason Cong, John Lee, Lieven Vandenberghe. 10-14 [doi]
- Multi-scenario buffer insertion in multi-core processor designsYifang Liu, Jiang Hu, Weiping Shi. 15-22 [doi]
- Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locationsBruce Tseng, Hung-Ming Chen. 23-30 [doi]
- Metal-density driven placement for cmp variation and routabilityTung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang. 31-38 [doi]
- Highly efficient gradient computation for density-constrained analytical placement methodsJason Cong, Guojie Luo. 39-46 [doi]
- Abacus: fast legalization of standard cell circuits with minimal movementPeter Spindler, Ulf Schlichtmann, Frank M. Johannes. 47-53 [doi]
- 3-D floorplanning using labeled tree and dual sequencesRenshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng. 54-59 [doi]
- Variations, margins, and statisticsPatrick McGuinness. 60-67 [doi]
- Implications of device timing variability on full chip timingEd Grochowski, Murali Annavaram, Paul Reed. 68 [doi]
- How to get real madAndrew B. Kahng. 69 [doi]
- A robust approach to lithography friendly design implementationPhiroze N. Parakh, Shankar Krishnamoorthy. 70 [doi]
- Fast interconnect synthesis with layer assignmentZhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay, Paul G. Villarrubia. 71-77 [doi]
- RF interconnects for communications on-chipM.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman. 78-83 [doi]
- Placement challenges for structured ASICsHerman Schmit, Amit Gupta, Radu Ciobanu. 84-86 [doi]
- A framework for layout-level logic restructuringHosung (Leo) Kim, John Lillis. 87-94 [doi]
- Optimizing non-monotonic interconnect using functional simulation and logic restructuringStephen Plaza, Igor L. Markov, Valeria Bertacco. 95-102 [doi]
- Reap what you sow: spare cells for post-silicon metal fixKai-Hui Chang, Igor L. Markov, Valeria Bertacco. 103-110 [doi]
- Optimal post-routing redundant via insertionKuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao. 111-117 [doi]
- Efficient multilayer routing based on obstacle-avoiding preferred direction steiner treeChih-Hung Liu, Yao-Hsin Chou, Shih-Yi Yuan, Sy-Yen Kuo. 118-125 [doi]
- An ::::O::::(::::n::::log::::n::::) edge-based algorithm for obstacle-avoiding rectilinear steiner tree constructionJieyi Long, Hai Zhou, Seda Ogrenci Memik. 126-133 [doi]
- Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extractionYu-Ning Chang, Yih-Lang Li, Wei-Tin Lin, Wen-Nai Cheng. 134-141 [doi]
- Issues in global routingWilliam Swartz. 142-147 [doi]
- The coming of age of (academic) global routingMichael D. Moffitt, Jarrod A. Roy, Igor L. Markov. 148-155 [doi]
- The ISPD global routing benchmark suiteGi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz. 156-159 [doi]
- Statistical timing analysis considering spatially and temporally correlated dynamic power supply noiseTakashi Enami, Shinyu Ninomiya, Masanori Hashimoto. 160-167 [doi]
- Stress aware layout optimizationVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal. 168-174 [doi]
- Discrete buffer and wire sizing for link-based non-tree clock networksRupak Samanta, Jiang Hu, Peng Li. 175-181 [doi]
- Activity and register placement aware gated clock network designWeixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu. 182-189 [doi]
- Automated design of digital microfluidic lab-on-chip under pin-count constraintsTao Xu, Krishnendu Chakrabarty. 190-198 [doi]
- Physical design issues in biofluidic microchipsTamal Mukherjee, Anton J. Pfeiffer, Steinar Hauan. 199 [doi]
- A high-performance droplet router for digital microfluidic biochipsMinsik Cho, David Z. Pan. 200-206 [doi]