Table of Contents

• On Line IC Test Course With Distance Access to Test EquipmentMiguel Angel Allende, Román Mozuelos, Mar Martínez, Salvador Bracho.
• Design for Testability Techniques: A Comparative AnalysisMiron Abramovici. 1
• Testing Embedded Core-Based System ChipsErik Jan Marinissen, Yervant Zorian. 2
• Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex CircuitsFabian Vargas 0001, Alexandre M. Amory. 6-12
• Upset-like fault injection in VHDL descriptions: A Method and Preliminary ResultsRaoul Velazco, A. Bragagnini, Oscar Calvo. 13-18
• A Software Tool for Simulating Single Event Upsets in a Digital Signal ProcessorPablo A. Ferreyra, Carlos A. Marqués, Javier P. Gaspar, Ricardo T. Ferreyra. 19-23
• Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case StudiedRaoul Velazco, Sana Rezgui, Haissam Ziade. 24-29
• A Test Calculation Principle for Logic and Timing FaultsJózsef Sziray. 32-37
• Dynamic Signal X-Y Zoning and its Applicability to Detect Time Critical Defects in the Digital DomainAnotnio Zenteno, Víctor H. Champac, Joan Figueras. 38-44
• Fault Modeling and Simulation at Behavioral LevelPaul Bizgambiglia, Dominique Federici, Jean François Santucci. 45-50
• Development of Self-Testing Software ComponentsLuciano Hayato Ukuma, Eliane Martins. 52-55
• A New Efficient Coordinated CheckpointingSérgio Luis Cechin, Ingrid Jansch-Pôrto. 56-61
• Deploying Fault-Tolerant Processing Services for Asynchronous Distributed SystemsLívia Maria Rodrigues Sampaio Campos, Francisco Vilar Brasileiro. 62-73
• Topological Considerations for the Diagnosability Conditions of Analogue CircuitsUsing a Pair of Conjugate TreesArturo Sarmiento-Reyes, Luis Hernadez Martinez. 76-79
• Filter Sensitivity Analysis Using the TRAMJosé Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski. 80-83
• Designing Testable Networks for Transfer Function RealizationJosé Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski, Antonio Carneiro de Mesquita Filho. 84-87
• Procedures for Selection of Validation Vectors on the Algorithm LevelVacius Jusas, Kestutis Paulikas, Rimantas Seinauskas. 90-95
• ATPG Driven Logic Synthesis for Delay and Power MinimizationIvor Ting, Andreas G. Veneris, Magdy S. Abadir. 96-99
• Sequential ATPG Using Combinational AlgorithmsMiron Abramovici, Xiaoming Yu, Elizabeth M. Rudnick. 100-106
• Mixed-signal RF Design-for-Test: Is It R (Real) or F (Fake)?Mani Soma. 107
• On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon AreaFlorence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell. 112-117
• Proposal of an Operation-Region Model for Analyzing Analog and Mixed-Signal CircuitsYukiya Miura. 118-125
• The Sigma-Delta-Bist Method Applied to Linear Analog CircuitsL. Cassol, Luigi Carro, Marcelo Lubaszewski. 126-130
• Innovative Built-In Self-Test Schemes for On-Chip Diagnosis, Compliant with the IEEE 1149.4 Mixed-Signal Test Bus StandardGladys Omayra Ducoudray Acevedo, Jaime Ramírez-Angulo. 131-134
• The Use of Analytical and Simulation Solutions with Statecharts for performance evaluation: A case study of a File Server modelCarlos Renato Lisboa Francês, Nandamudi Lankalapalli Vijaykumar, Regina Helena Carlucci Santana, Marcos José Santana, Solon Venâncio de Carvalho, Vakulathil Abdurahiman. 136-141
• On the Evaluation of heartbeat-like DetectorsLuiz Angelo Barchet-Estefanel, Ingrind Jansch-Porto. 142-147
• Evaluating Approaches of Information Capturing from Applications InformationAdriano Brum Fontoura, Ingrid Jansch-Pôrto, Sérgio Luis Cechin. 148-153
• Multiple Scan Chain Design for Two-Pattern TestingIlia Polian, Bernd Becker 0001. 156-161
• Design Error Diagnosis in Scan-Path DesignsRaimund Ubar. 162-168
• Improved Methods for Fault Diagnosis in Scan-Based BISTIsmet Bayraktaroglu, Alex Orailoglu. 169-172
• Failure Safe PLD Based Control SystemJorge Marcos, Jacobo Álvarez, Enrique Mandado, Andres Nogueiras. 174-179
• Dynamically Rotate And Free for Test: The Path for FPGA Concurrent TestManuel G. Gericota, Gustavo R. Alves. 180-185
• 3DB Challange for DfT, DfM, DOT & BIST Integration into Analogue and Mixed Signal ICsAndreas Lechner, Martin John Burbidge, Andrew Richardson 0001, B. Hermes. 194-199
• An Analog-based Approach for MEMS TestingBernard Courtois, Salvador Mir, Benoît Charlot, Marcelo Lubaszewski. 200-203
• IEEE 1149.1- The Internet of TestDave Bonnett. 204-208
• Test Challenges in a Nanometric WorldJoan Figueras. 209
• A Test Method for a Broad Class of DSP CircuitsÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski. 214-219
• Using On-Chip Monitors in Testing CPU MicroarchitectureJanusz Sosnowski, Rafal Jurkiewicz. 220-225
• Orienting Redundancy and HW/SW Codesign Techniques Towards Speech Recognition SystemsFabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.. 226-233
• A Timed Calculus for ATG-Based Timing Analysis with Complex GatesJosé Luís Güntzel, Ana Cristina Medina Pinto, Ricardo Reis 0001. 234-239
• A Formal Test Set for RNS Adders and an Efficient Low Power BIST SchemeHaridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou. 242-247
• Designing and Implementing Efficient BISR Techniques for Embedded RAMsMichael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian. 248-252
• Electrical Analysis of Gate Oxide Short in MOS TechnologiesMichel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand. 266-272
• Test of Data Retention Faults Sensing the Bit Line with a DFT Bases Differential AmplifierVíctor H. Champac, Victor Avendaño, Gordana Jovanovic-Dolecek. 273-276
• Testing Fault Tolerance Mechanisms in DBMS Through Fault InjectionLuis C. R. Gonçalves, Paulo R. Rodegheri, Ricardo Augusto Manfredini, Taisy Silva Weber. 278-284
• Generalized Distributed Comparison-Based System-Level DiagnosisLuiz Carlos Pessoa Albini, Elias P. Duarte Jr., Leonardo L. Giovanini, Marie-Lise Flottes, Christian Landrault, A. Petitqueux. 285-290