Table of Contents

• Placement Optimization via PPA-Directed Graph ClusteringYi-Chen Lu, Tian Yang, Sung Kyu Lim, Haoxing Ren. 1-6 [doi]
• From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing PredictionVidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar. 7-14 [doi]
• Faster FPGA Routing by Forecasting and Pre-Loading Congestion InformationUmair F. Siddiqi, Timothy Martin, Sam Van Den Eijnden, Ahmed Shamli, Gary Gréwal, Sadiq M. Sait, Shawki Areibi. 15-20 [doi]
• Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse RewardsYannick Uhlmann, Michael Essich, Lennart Bramlage, Jürgen Scheible, Cristóbal Curio. 21-26 [doi]
• LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional SubspacesShuhan Zhang, Fan Yang 0001, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 27-34 [doi]
• RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RLWei Shi, Hanrui Wang 0002, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han 0003, Nan Sun. 35-41 [doi]
• Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement LearningHung-Yun Hsu, Mark Po-Hung Lin. 43-48 [doi]
• The Changing Landscape of AI-driven System Optimization for Complex Combinatorial OptimizationSomdeb Majumdar. 49 [doi]
• AI Chips Built by AI - Promise or Reality?: An Industry PerspectiveThomas Andersen. 51 [doi]
• ML for Analog Design: Good Progress, but More to DoBorivoje Nikolic. 53-54 [doi]
• SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery NetworksBing-Yue Wu, Shao-Yun Fang, Hsiang-Wen Chang, Peter Wei. 55-61 [doi]
• XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine LearningVidya A. Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany. 63-69 [doi]
• Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net ArchitectureYonghwi Kwon 0002, Youngsoo Shin. 71-76 [doi]
• Efficient Design Rule Checking Script Generation via Key Information ExtractionBinwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu 0001, Martin D. F. Wong. 77-82 [doi]
• Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement LearningNaiju Karim Abdul, George Antony, Rahul M. Rao, Suriya T. Skariah. 83-90 [doi]
• Autoencoder-Based Data Sampling for Machine Learning-Based Lithography Hotspot DetectionMohamed Tarek Ismail, Hossam Sharara, Kareem Madkour, Karim Seddik. 91-96 [doi]
• Driving Early Physical Synthesis Exploration through End-of-Flow Total Power PredictionYi-Chen Lu, Wei-Ting Chan, Vishal Khandelwal, Sung Kyu Lim. 97-102 [doi]
• Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency ScalingChristopher A. Metz, Mehran Goli, Rolf Drechsler. 103-109 [doi]
• A Thermal Machine Learning Solver For Chip SimulationRishikesh Ranade, Haiyang He, Jay Pathak, Norman Chang, Akhilesh Kumar, Jimin Wen. 111-117 [doi]
• Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML AlgorithmsHadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Sayak Kundu, Rohan Mahapatra, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang, Ziqing Zeng. 119-126 [doi]
• Graph Representation Learning for Gate Arrival Time PredictionPratik Shrestha, Saran Phatharodom, Ioannis Savidis. 127-133 [doi]
• A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design AutomationZixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan. 135-141 [doi]
• Industrial Experience with Open-Source EDA ToolsChristian Lück, Daniela Sanchez Lopera, Sven Wenzek, Wolfgang Ecker. 143 [doi]
• Invertible Neural Networks for Design of Broadband Active MixersOluwaseyi Akinwande, Osama Waqar Bhatti, Xingchen Li, Madhavan Swaminathan. 145-151 [doi]
• High Dimensional Optimization for Electronic DesignYuejiang Wen, Jacob Dean, Brian A. Floyd, Paul D. Franzon. 153-157 [doi]
• Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural NetworksZhengfeng Wu, Ioannis Savidis. 159-165 [doi]
• RxGAN: Modeling High-Speed Receiver through Generative Adversarial NetworksPriyank Kashyap, Archit Gajjar, Yongjin Choi, Chau-Wai Wong, Dror Baron, Tianfu Wu, Chris Cheng, Paul D. Franzon. 167-172 [doi]