Abstract is missing.
- A DRAM Compiler for Fully Optimized Memory InstancesG. Harling. 3-8 [doi]
- Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact SchemeKyung-Saeng Kim, KwangMyoung Rho, Kwyro Lee. 9-12 [doi]
- Design of an Embedded Fully-Depleted SOI SRAMRaymond J. Sung, John C. Koob, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn. 13 [doi]
- A P1500 Compliant Programable BistShell for Embedded MemoriesSandeep Koranne, Tom Waayers, Robert Beurze, Clemens Wouters, Sunil Kumar, G. S. Visweswara. 21-28 [doi]
- BIST-Based Bitfail Mapping of an Embedded DRAMBrian R. Kessler, Jeffrey Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho. 29 [doi]
- A Method to Caculate Redundancy Coverage for FLASH MemoryS. Matarrese, L. Fasoli. 41-44 [doi]
- An Error Control Code Scheme for Multilevel Flash MemoriesStefano Gregori, Guido Torelli, Osama Khouri, Rino Micheloni. 45-50 [doi]
- An Approach for Evaluation of Redunancy Analysis AlgorithmsSamvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian. 51 [doi]
- Transient Faults in DRAMs: Concepts, Analysis and Impact on TestsZaid Al-Ars, A. J. van de Goor. 59-64 [doi]
- Realistic Fault Models and Test Procedures for Multi-Port SRAMsSaid Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers. 65-72 [doi]
- A Parallel Approach for Testing Multi-Port Static Random Access MemoriesFarzin Karimi, Fabrizio Lombardi, V. Swamy Irrinki, T. Crosby. 73 [doi]
- Equivalence Checking a 256MB SDRAMSimon Napper, Dian Yang. 85-90 [doi]
- Testing Carry Logic Modules of SRAM-based FPGAsXiaoling Sun, Jian Xu, Pieter M. Trouborst. 91-98 [doi]
- Low Output Resistance Charge Pump for Flash Memory ProgrammingOsama Khouri, Stefano Gregori, Dario Soltesz, Guido Torelli, Rino Micheloni. 99 [doi]