Abstract is missing.
- Workshop Organizing Committee [doi]
- Acknowledgement [doi]
- Program Committee [doi]
- Preface [doi]
- A Study of Architecture Description Languages from a Model-based PerspectiveWei Qin, Sharad Malik. 3-11 [doi]
- An Introduction to the Plasma LanguageBrian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt. 12-22 [doi]
- On SAT-based Bounded Invariant Checking of Blackbox DesignsMarc Herbstritt, Bernd Becker. 23-28 [doi]
- PaMira - A Parallel SAT Solver with Knowledge SharingTobias Schubert, Matthew D. T. Lewis, Bernd Becker. 29-36 [doi]
- Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test SetsPaolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero. 37-41 [doi]
- Post-Verification Debugging of Hierarchical DesignsMoayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler. 42-47 [doi]
- An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected DefectsJennifer Dworak. 48-54 [doi]
- Exploiting an I-IP for both Test and Silicon Debug of Microprocessor CoresPaolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 55-62 [doi]
- Is IDDQ Test of Microprocessors Feasible?Bin Xue, D. M. H. Walker. 63-69 [doi]
- A Pseudo-Deterministic Functional ATPG based on EFSM TraversingGiuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli. 70-75 [doi]
- Simulation Data Mining for Functional Test Pattern JustificationCharles H.-P. Wen, Li-C. Wang. 76-83 [doi]
- Search-Space Optimizations for High-Level ATPGJorge Campos, Hussain Al-Asaad. 84-89 [doi]
- A TDM Test Scheduling Method for Network-on-Chip SystemsJohn Mark Nolen, Rabi N. Mahapatra. 90-98 [doi]
- Automated Extraction of Structural Information from SystemC-based IP for ValidationDavid Berner, Hiren D. Patel, Deepak Mathaikutty, Sandeep K. Shukla. 99-104 [doi]
- Pre-Silicon Validation of IPF Memory Ordering for Multi-Core ProcessorsSoohong P. Kim. 105-110 [doi]
- Automatic Generation of High Performance Embedded Memory Models for PowerPC MicroprocessorsJayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova. 111-118 [doi]
- Language-driven Validation of Pipelined Processors using Satisfiability SolversPrabhat Mishra, Heon-Mo Koo, Zhuo Huang. 119-126 [doi]
- On PSL Properties Re-use in SoC Design Flow Based on Transaction Level ModelingNicola Bombieri, Andrea Fedeli, Franco Fummi. 127-132 [doi]
- HW/SW Co-Verification of a RISC CPU using Bounded Model CheckingDaniel Große, Ulrich Kühne, Rolf Drechsler. 133-137 [doi]
- Retiming Verification Using Sequential Equivalence CheckingBrian Kahne, Magdy S. Abadir. 138-142 [doi]