Abstract is missing.
- Hierarchical Timing-Critical Paths Analysis in Sequential CircuitsLembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin. 1-6 [doi]
- Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA DesignsRoberto Sierra, Carlos Carreras, Gabriel Caffarena. 7-12 [doi]
- A 40nm Critical Path Monitor for the Detection of Setup and Hold Time ViolationsHernan Aparicio, Pablo Ituero. 13-18 [doi]
- VCO Verilog AMS Model for Fast Simulation in VCO-Based ADCDavid Buffeteau, Dominique Morche, Jose-Luis Gonzalez Jimenez. 19-22 [doi]
- Mobile Terminals System-Level Memory Exploratio for Power and Performance OptimizationAmal Ben Ameur, Michel Auguin, François Verdier, Valerio Frascolla. 23-28 [doi]
- Enhanced RF Harvesting System by the Utilization of Resonant CavitiesGuillem Martinez de Arriba, Ertugrul Coskuner, Joan J. Garcia-Garcia. 29-31 [doi]
- Memory Access Pattern Profiling for Streaming Applications Based on MATLAB ModelsThomas Goldbrunner, Thomas Wild, Andreas Herkersdorf. 32-38 [doi]
- Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard ApplicationsHimadri Singh Raghav, Vivian A. Bartlett, Izzet Kale. 39-45 [doi]
- A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level DesignsJohannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey. 46-53 [doi]
- Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCsP. Anagnostou, A. Gomez, Pascal A. Hager, Hamed Fatemi, José Pineda de Gyvez, Lothar Thiele, Luca Benini. 54-61 [doi]
- A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID ApplicationsAsghar Bahramali, Marisa López-Vallejo. 62-67 [doi]
- A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power TransferRemi Dekimpe, Pengcheng Xu, Maxime Schramme, Denis Flandre, David Bol. 68-75 [doi]
- A Reliable PUF in a Dual Function SRAMMohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski. 76-81 [doi]
- Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI TechnologyEnrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández. 82-87 [doi]
- Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy ManagementRida Kheirallah, Jean Marc Galliere, Nadine Azémard, Gilles R. Ducharme. 88-91 [doi]
- Optical and Electrical Simulations of Radiation-Hard Photodiode in 0.35μM High-Voltage CMOS TechnologyFilip Segmanovic, Frederic Roger, Gerald Meinhard, Ingrid Jonak-Auer, Tomislav Suligoj. 92-96 [doi]
- UVM-Based Verification of a Mixed-Signal Design Using SystemVerilogNikolaos Georgoulopoulos, Ioannis Giannou, Alkiviadis A. Hatzopoulos. 97-102 [doi]
- Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLSJulian Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López. 103-110 [doi]
- VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic DesignSachin Maheshwari, Vivian A. Bartlett, Izzet Kale. 111-117 [doi]
- Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy HarvestingM. Pilar Garde, Antonio J. López-Martín, Daniel Orradre, Jaime Ramírez-Angulo. 118-122 [doi]
- FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoCGuillaume Patrigeon, Pascal Benoit, Lionel Torres. 123-128 [doi]
- A Multi-Level Power-on Reset for Fine-Grained Power ManagementAndres Amaya, Luis E. Rueda G, Elkim Roa. 129-132 [doi]
- Reservoir Computing Hardware for Time Series ForecastingErik S. Skibinsky-Gitlin, Miquel L. Alomar, Eugeni Isern, Miquel Roca, Vincent Canals, Josep L. Rosselló. 133-139 [doi]
- Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage VariabilityA. K. M. Mahfuzul Islam, Hidetoshi Onodera. 140-146 [doi]
- Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415Moisés Herrera, Tingyu Wang, Peter A. Beerel. 147-154 [doi]
- TSV Assignment of Thermal and Wirelength Optimization for 3D-IC RoutingYi Zhao, Cong Hao, Takeshi Yoshimura. 155-162 [doi]
- Effect of Temperature Variation in Experimental DPA and DEMA AttacksErica Terra-Sanchez, Antonio J. Acosta. 163-168 [doi]
- Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS GatesSotirios K. Goudos, Nikolaos Karagiorgos, Maria Ntogramatzi, Ioannis Messaris, Spyridon Nikolaidis. 169-176 [doi]
- Multiclass Network Attack Classifier Using CNN Tuned with Genetic AlgorithmsRoberto Blanco, Pedro Malagón, Juan J. Cilla, José Manuel Moya. 177-182 [doi]
- Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State MachinesVassilis Paliouras, Konstantina Karagianni, Yann Oster. 183-190 [doi]
- Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge NetworkIbrahim A. Bello, Basel Halak, Mohammed El-Hajjar, Mark Zwolinski. 191-197 [doi]
- MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core SystemsAli Aalsaud, Haider Alrudainy, Rishad A. Shafik, Fei Xia, Alex Yakovlev. 198-205 [doi]
- Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous SystemsAli Aalsaud, Ashur Rafiev, Fei Xia, Rishad A. Shafik, Alex Yakovlev. 206-213 [doi]
- Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D IntegrationLennart Bamberg, Alberto García Ortiz. 214-221 [doi]
- Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual ChannelsLennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz. 222-228 [doi]
- Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor DesignsMonir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris. 229-236 [doi]
- Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory StructureHongjie Xu, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 237-242 [doi]
- Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT DevicesRuzica Jevtic, Marko Ylitolva, Lauri Koskinen. 243-247 [doi]
- A Systematic Performance Comparison of Ultra Low-Power AES S-BoxesThomas Vandenabeele, Roel Uytterhoeven, Wim Dehaene, Nele Mentens. 248-253 [doi]
- Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD DisplaysKonstantinos Oikonomou, Orestis Theodorakopoulos, Georgios Keramidas, Georgios Theodoridis. 254-260 [doi]