Table of Contents

• A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear EqualizerShraman Mukherjee, Sumantra Seth, Saurabh Saxena. 1-5 [doi]
• 2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOsJaved S. Gaggatur, Miryala Chandra Shekar, Komal Deshmukh. 6-10 [doi]
• A PC based Ultrasound back-end signal processor using Intel® Performance PrimitivesJayaraj U. Kidav, Akula Sri Rama Pavan, M. Rajesh, Navin Kumar. 11-15 [doi]
• Power and Energy Safe Real-Time Multi-Core Task SchedulingKalyan Baita, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst, Xiaoqing Wen. 16-21 [doi]
• Equivalence Checking of Non-Binary Combinational NetlistsAditi Singh. 22-27 [doi]
• Dynamic Variable Ordering during Algebraic Backward Rewriting for Formal Verification of MultipliersJitendra Kumar, Asutosh Srivastava. 28-32 [doi]
• o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature SensorsArpan Jain, Abhishek Pullela, Ashfakh Ali, Zia Abbas. 33-38 [doi]
• A Real Time Multi-Bit DAC Mismatch Estimation & Correction Technique For Wideband Continuous Time Sigma Delta ModulatorsAnkur Bal, Sharad Gupta, Rupesh Singh. 39-43 [doi]
• A 10 Gb/s On-chip Jitter Measurement Circuit Based on Transition Region Scanning MethodSantunu Sarangi, Indranil Som, T. K. Bhattacharyya. 44-49 [doi]
• Customizable Head-mounted Device for Detection of Eye Disorders using Virtual RealityY. Pawan Kumar Gururaj, Sai Anirudh Karre, Raghav Mittal, Y. Raghu Reddy, Syed Azeemuddin. 50-55 [doi]
• Energy Aware Dynamic Load Balancer for Embedded Multi-core SystemsSachin Ramesh Pundkar, Surajit Pradeep Karmakar, Samir Kumar Mishra, Surendra Singh, Tushar Vrind. 56-61 [doi]
• Energy Optimized Non-preemptive Scheduling of Real-Time Tasks with Precedence and Reliability ConstraintsNiraj Kumar 0004, Arijit Mondal. 62-67 [doi]
• MLIR: Machine Learning based IR Drop Prediction on ECO Revised Design for Faster ConvergenceSantanu Kundu, Manoranjan Prasad, Sashank Nishad, Sandeep Nachireddy, Harikrishnan K. 68-73 [doi]
• NanoLeak: A Fast Analytical Green's Function-based Leakage-aware Thermal SimulatorAnjali Agrawal, Smruti R. Sarangi. 74-79 [doi]
• Automated Debugger for Optimum Physical Clock Structure Targeting Minimal LatencyRushabh Shah, Krishna Agrawal, G. Anjaneyulu, Vishnu Bhaskari. 80-85 [doi]
• Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC FrameworkM. K. Aparna Nair, Police Manoj Kumar Reddy, Y. L. Abijith, Venkatesh Rajagopalan, Soumya J.. 86-91 [doi]
• Scalable Hybrid Cache Coherence Using Emerging Links for Chiplet ArchitecturesSri Harsha Gade, Mitali Sinha, Madhur Kumar, Sujay Deb. 92-97 [doi]
• Novel Circuit Architecture for configurable eDP and MIPI DPHY IOSunil Kumar C. R, Aruna Kumar, Sanjib Basu. 98-101 [doi]
• MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix MultiplicationM. R. Ashuthosh, Santosh Krishna, Vishvas Sudarshan, Srinivasan Subramaniyan, Madhura Purnaprajna. 102-107 [doi]
• An Attack Resilient PUF-based Authentication Mechanism for Distributed SystemsMohammad Ebrahimabadi, Mohamed F. Younis, Wassila Lalouani, Naghmeh Karimi. 108-113 [doi]
• Static Malware Analysis using ELF features for Linux based IoT devicesAkshara Ravi, Vivek Chaturvedi. 114-119 [doi]
• HeapSafe: Securing Unprotected Heaps in RISC-VAsmit De, Swaroop Ghosh. 120-125 [doi]
• SEVA: Structural Analysis based Security Evaluation of Sequential LockingAbdulrahman Alaql, Aritra Dasgupta, Md Moshiur Rahman 0001, Swarup Bhunia. 126-131 [doi]
• Tracking Coverage Artefacts for Periodic Signals using Sequence-based AbstractionsAyan Chakraborty, Sayandeep Sanyal, Pallab Dasgupta, Aritra Hazra, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian. 132-137 [doi]
• Stitch-avoiding Global Routing for Multiple E-Beam LithographyKritanta Saha, Sudipta Paul 0001, Pritha Banerjee, Susmita Sur-Kolay. 138-143 [doi]
• Robust Estimation of FPGA Resources and Performance from CNN ModelsPingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia. 144-149 [doi]
• Identifying Combination of Defects and Unknown Defects on Semiconductor Wafers using Deep Learning and Hierarchical ReclusteringAnkit Gupta 0010, Adrita Barari, Damini, Keerthi Kiran Jagannathachar, Seungwoo Lee, Janghoon Oh, Jungha Kim, Min-Joo Kim. 150-155 [doi]
• An Architectural support for Digital Microfluidic based Hot-Spot free ComputingSumanta Pyne. 156-161 [doi]
• Hardware Accelerator for Capsule Network based Reinforcement LearningDola Ram, Suraj Panwar, Kuruvilla Varghese. 162-167 [doi]
• SCENIC: An Area and Energy-Efficient CNN-based Hardware Accelerator for Discernable Classification of Brain Pathologies using MRIBodepu Sai Tirumala Naidu, Shreya Biswas, Rounak Chatterjee, Sayak Mandal, Srijan Pratihar, Ayan Chatterjee, Arnab Raha, Amitava Mukherjee, Janet Paluh. 168-173 [doi]
• Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural NetworksNeelam Surana, Pramod Kumar Bharti, Bachu Varun Tej, Joycee Mekie. 174-179 [doi]
• Towards a Fully Autonomous UAV Controller for Moving Platform Detection and LandingMichalis Piponidis, Panayiotis Aristodemou, Theocharis Theocharides. 180-185 [doi]
• A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing ApplicationsAdithya Sunil Edakkadany, Kuntal Desaiz, Abhishek Srivastavay. 186-191 [doi]
• A Low Phase Noise 30 GHz Oscillator Topology for Resonant-Fin-Transistors Based High-Q On-chip Resonators in 14 nm TechnologyAbhishek Srivastava 0002, Baibhab Chatterjee, Dana Weinstein, Shreyas Sen. 192-197 [doi]
• Design Methodology of Low Phase Noise mmWave Oscillator with Partial Cancellation of Static Capacitance of High-Q On-chip MEMS ResonatorAshish Papreja, Sresthavadhani Mantha, Abhishek Srivastava. 198-203 [doi]
• An event driven approximate bio-electrical model generating surface electromyography RMS featuresK. Vinay, Vikas Vazhayil, Madhav Rao. 204-209 [doi]
• Approximate Adders for Deep Neural Network AcceleratorsS. Raghuram, N. Shashank. 210-215 [doi]
• 40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention ModeKedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet. 216-221 [doi]
• Low Power and Area Efficient Approximate 2D-DCT Architecture for Wireless Capsule EndoscopyVaibhavi Solanki, Rahul Ranjan Kumar, Praveen Ghagare, Anand D. Darji. 222-227 [doi]
• Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOIChandan Kumar, Rahul Kumar, Anuj Grove, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat. 228-233 [doi]
• Criticality based Reliability from Rowhammer Attacks in Multi-User-Multi-FPGA PlatformKrishnendu Guha, Amlan Chakrabarti. 234-239 [doi]
• Pulse-width Modulation Technique for Generation of Multiple Analog Voltages for On-chip CalibrationRajath Vasudevamurthy. 240-245 [doi]
• Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance CheckingHabibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta 0001, Debesh K. Das, Bhargab B. Bhattacharya. 246-251 [doi]
• Parasitic Interactions with Intermediate Substrates and Methods to Mitigate their Impact: A Case Study in Voltage Protection ICsSrinivasa Prasad Soundararajan, Harry Gee, Adam Whitworth. 252-256 [doi]
• A High Voltage Level Shifter for Automotive Buck Converter with a Fast Transient ResponseAnupama Deo, Ashis Maity, Amit Patra. 257-262 [doi]
• A Soft RISC-V Vector Processor for Edge-AIV. Naveen Chander, Kuruvilla Varghese. 263-268 [doi]
• Design of 8-bit Dadda Multiplier using Gate Level Approximate 4: 2 CompressorKattekola Naresh, Y. Padma Sai, Shubhankar Majumdar. 269-274 [doi]
• DeepQMLP: A Scalable Quantum-Classical Hybrid Deep Neural Network Architecture for ClassificationMahabubul Alam, Swaroop Ghosh. 275-280 [doi]
• Image Completion using a Sparse Probabilistic Spin Logic NetworkAmina Haroon, Sneh Saurabh. 281-286 [doi]
• Threshold Voltage Modeling of Negative Capacitance Double Gate TFETU. S. Shikha, Rekha K. James, Anju Pradeep, Sumi Baby, Jobymol Jacob. 287-291 [doi]
• Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G ApplicationsJyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta. 292-296 [doi]
• How Good Silicon Oxide-based Memristor Can be?Mani Shankar Yadav, Avinash Kumar Gupta, Kanupriya Varshney, Brajesh Rawat. 297-302 [doi]
• Role of Interface Trap Charges in the Performance of Monolayer and Bilayer MoS2-based Field-Effect TransistorsAkhilesh Rawat, Anjali Goel, Brajesh Rawat. 303-308 [doi]