Niranjan M. Devashrayee - researchr alias

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Viewing Publication 1 - 6 from 6

2011

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A SurveyUsha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee. vlsi, 2011, 2011. [doi]

2010

Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based CodesUsha S. Mehla, Kankar S. Dasgupta, Niranjan M. Devashrayee. vlsid 2010: 33-38 [doi]

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area OverheadUsha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta. isvlsi 2010: 448-449 [doi]

Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A SurveyUsha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee. vlsi, 2010, 2010. [doi]

Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overheadUsha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee. apccas 2010: 40-43 [doi]

Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression methodUsha Sandeep Mehta, Niranjan M. Devashrayee, Kanker S. Dasgupta. issoc 2010: 1-7 [doi]

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