Abstract is missing.
- Automatic Mapping of Parallel Applications onto Multi-Processor Platforms: A Multimedia ApplicationPierre G. Paulin. 2-4 [doi]
- Reliability and Power Management of Integrated SystemsKresimir Mihic, Tajana Simunic, Giovanni De Micheli. 5-11 [doi]
- Functional Validation of Programmable ArchitecturesPrabhat Mishra, Nikil D. Dutt. 12-19 [doi]
- Long Term Trends for Embedded System DesignAhmed Amine Jerraya. 20-26 [doi]
- System-Level Power OptimizationWolfgang Nebel. 27-34 [doi]
- Life-Inspired SystemsLech Józwiak. 36-43 [doi]
- Implicit vs. Explicit Resource Allocation in SMT ProcessorsFrancisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero. 44-51 [doi]
- Design Methodology Innovations Address Manufacturing Technology Challenges: Power and PerformanceUlf Schlichtmann. 52-59 [doi]
- Arithmetic Coding Architecture for H.264/AVC CABAC Compression SystemRoberto R. Osorio, Javier D. Bruguera. 62-69 [doi]
- A Simple Micro-Threaded Data-Driven ProcessorAhmet Bindal, Silvio Brugada, T. Ha, Willie Sana, Mandeep Singh, Vinilkant Tejaswi, David Wyland. 70-77 [doi]
- A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic CircuitsTurgay Temel, Avni Morgul, Nizamettin Aydin. 80-87 [doi]
- Memory Aware HLS and the Implementation of Ageing VectorsGwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin. 88-95 [doi]
- A Complete Methodology for Memory Optimization in DSP ApplicationsFlorian Marteil, Nathalie Julien, Eric Senn, Eric Martin. 98-103 [doi]
- ASSEC: An Asynchronous Self-Checking RISC-based ProcessorP. D. Hyde, G. Russell. 104-111 [doi]
- Investigating Available Instruction Level Parallelism for Stack Based Machine ArchitecturesHuibin Shi, Chris Bailey. 112-120 [doi]
- A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack MachinesChris Bailey. 121-129 [doi]
- Compiler-Directed Dynamic Memory Disambiguation for Loop StructuresSoyeb Alli, Chris Bailey. 130-134 [doi]
- Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary AlgorithmsMariusz Rawski, Henry Selvaraj, Pawel Morawiecki. 136-143 [doi]
- Cost-Efficient Implementation of Adaptive Finite State MachinesMaik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke. 144-151 [doi]
- Boolean Minimizer FC-Min: Coverage Finding ProcessPetr Fiser, Hana Kubatova. 152-159 [doi]
- An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment MethodsLech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk. 160-167 [doi]
- BDD Circuit Optimization for Path Delay Fault TestabilityGörschwin Fey, Junhao Shi, Rolf Drechsler. 168-172 [doi]
- A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code DecoderPasquale Ciao, Giulio Colavolpe, Luca Fanucci. 174-181 [doi]
- VLSI Design of a Digital RFI Cancellation Scheme for VDSL TransceiversLuca Fanucci, Riccardo Locatelli, Esa Petri. 182-189 [doi]
- Shift Invert Coding (SINV) for Low Power VLSIJayapreetha Natesan, Damu Radhakrishnan. 190-194 [doi]
- Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal ApplicationsJeffrey McFiggins, Marie Yvanoff, Jayanti Venkataraman. 195-199 [doi]
- IP-Block Based Integration of Very High Performance WLAN ModemJussi Roivainen, Jukka Rautio. 200-207 [doi]
- {2:::n:::+1, s:::n+k:::, s:::n:::-1}: A New RNS Moduli Set ExtensionRicardo Chaves, Leonel Sousa. 210-217 [doi]
- Image Processing Algorithms on Reconfigurable Architecture using HandelCMuthukumar Venkatesan, Daggu Venkateshwar Rao. 218-226 [doi]
- Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy CoderImed Aouadi, Omar Hammami. 227-233 [doi]
- On the Packet-Switched Implementation of a Discrete-Time CNNSuleyman Malki, Lambert Spaanenburg. 234-241 [doi]
- Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAsLuo Jianwen, Jong Ching Chuen. 244-248 [doi]
- Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson IterationUmut Küçükkabak, Ahmet Akkas. 249-253 [doi]
- Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number SystemsFaisal M. Khan, Mark G. Arnold, William M. Pottenger. 254-261 [doi]
- Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4Ali R. Iranpour, Krzysztof Kuchcinski. 262-269 [doi]
- Memory Requirement Optimization with Loop Fusion and Loop ShiftingQubo Hu, Martin Palkovic, Per Gunnar Kjeldsberg. 272-278 [doi]
- Multi-log Processor - Towards Scalable Event-Driven MultiprocessorsVinod Viswanath. 279-286 [doi]
- Information Trans-Coders in Information-Driven Circuit SynthesisLech Józwiak, Szymon Bieganski. 288-397 [doi]
- Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed CompilationS. F. Nielsen, Jens Sparsø, Jan Madsen. 298-305 [doi]
- A Constraints Programming Approach to Communication Scheduling on SoPC ArchitecturesChristophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale. 308-315 [doi]
- Easy SoC Design with VCI SystemC AdaptersSalim Ouadjaout, Dominique Houzet. 316-323 [doi]
- Multi-Pipeline Implementations of Real-Time Vector DFTAlexander A. Petrovsky, Sergei L. Shkredov. 326-333 [doi]
- Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-DecodersFilippo Speziali, Julien Zory. 334-341 [doi]
- Pipeline-Level Control of Self-Resetting PipelinesAbdel Ejnioui, Abdelhalim Alsharqawi. 342-349 [doi]
- An Energy-Efficient Adaptive Multiple-Issue ArchitectureMars Lan, Morteza Biglari-Abhari. 350-357 [doi]
- A High Speed FPGA Implementation of the Rijndael AlgorithmRefik Sever, A. Neslin Ismailoglu, Yusuf Çagatay Tekmen, Murat Askar, Burak Okcan. 358-362 [doi]
- Mixed Synchronous/Asynchronous State Memory for Low Power FSM DesignCao Cao, Bengt Oelmann. 363-370 [doi]
- A Formal Verification Methodology for IP-based DesignsDaniel Karlsson, Petru Eles, Zebo Peng. 372-379 [doi]
- Diminished-1 Modulo 2:::n::: + 1 Squarer DesignHaridimos T. Vergos, Costas Efstathiou. 380-386 [doi]
- Handel-C implementation of Classical Component Labelling AlgorithmMiroslaw Jablonski, Marek Gorgon. 387-393 [doi]
- Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGADavid Elléouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin. 394-401 [doi]
- Mapping of High-Level SDL Models to Efficient Implementations for TinyOSDaniel Dietterle, Jerzy Ryman, Kai F. Dombrowski, Rolf Kraemer. 402-406 [doi]
- A Heuristic for Wiring-Aware Built-In Self-Test SynthesisAbdil Rashid Mohamed, Zebo Peng, Petru Eles. 408-415 [doi]
- The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated DataAlexander V. Drozd, R. Al-Azzeh, J. V. Drozd, M. V. Lobachev. 416-423 [doi]
- Scene Management Models and Overlap Tests for Tile-Based RenderingIosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha. 424-431 [doi]
- Evaluation of Transient Fault Susceptibility in Microprocessor SystemsPiotr Gawkowski, Janusz Sosnowski. 432-439 [doi]
- Topological BDP Fault Simulation MethodVladimir Hahanov, Irina Hahanova, Stanley Hyduke. 440-443 [doi]
- Techniques for Formal Verification of Digital Systems: A System ApproachHamid Shojaei, Habib Ghayoumi. 444-449 [doi]
- Efficient Rapid Prototyping of Image and Video Processing AlgorithmsSalvatore Vitabile, Antonio Gentile, Sabato Marco Siniscalchi, Filippo Sorbello. 452-458 [doi]
- A Distributed Arithmetic Online Rotator for Signal Processing ApplicationsRobert Prain, Andrew P. Paplinski. 459-466 [doi]
- FPGA Based Design of the Railway s Interlocking EquipmentsRadek Dobias, Hana Kubatova. 467-473 [doi]
- CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-ChipVíctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Pedro P. Carballo, Wido Kruijtzer. 476-483 [doi]
- Modeling a Network Processor Using Object Oriented TechniquesLiam Noonan, Colin Flanagan. 484-490 [doi]
- An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-ChipNikolay Kavaldjiev, Gerard J. M. Smit. 492-498 [doi]
- Interesting Applications of Atmel AVR MicrocontrollersStanislav Korbel, Vlastimil Jánes. 499-506 [doi]
- A Fast and Well-Structured MultiplierJung-Yup Kang, Jean-Luc Gaudiot. 508-515 [doi]
- Fast Reconfigurable Hardware for the M-ary Modular ExponentiationLuiza de Macedo Mourelle, Nadia Nedjah. 516-523 [doi]
- Towards New Real-Time Processor: The Multioperand MSB-First Real-Time AdderKuspriyanto, Yusrila Y. Kerlooza. 524-529 [doi]
- Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor PlatformJari Kreku, Jani Penttilä, Janne Kangas, Juha-Pekka Soininen. 532-539 [doi]
- An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits DesignIvan Blunno, Guy Alain Narboni, Claudio Passerone. 540-547 [doi]
- An Efficient Exponential Algorithm with Exponential Convergence RateChichyang Chen, Kuo-Sheng Cheng. 548-555 [doi]
- What to Adapt in a High-Performance MicroprocessorPedro Trancoso. 556-563 [doi]
- DCP: A New Data Collection Protocol for Bluetooth-Based Sensor NetworksMatthias Handy, Frank Grassert, Dirk Timmermann. 566-573 [doi]
- Hybrid Greedy/Face Routing for Ad-Hoc Sensor NetworkJianhong Li, Laxmi Gewali, Henry Selvaraj, Muthukumar Venkatesan. 574-578 [doi]
- Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation SchemeMatthew D Souza, Adam Postula. 579-586 [doi]
- Phased Array and Adaptive Antenna Transceivers in Wireless Sensor NetworksRuimin Huang, Yiannos Manoli. 587-592 [doi]
- Addressing architecture for Brain-like Massively Parallel ComputersAbey Abraham Cohen. 594-597 [doi]
- A Mechanism for Implementing Precise Exceptions in Pipelined ProcessorsSoyeb Alli, Chris Bailey. 598-602 [doi]
- Implementation of Multiple-Valued Flip-Flips Using Pass Transistor LogicHafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam. 603-606 [doi]
- Dynamic Filter Cache for Low Power Instruction Memory HierarchyKugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya. 607-610 [doi]
- Area Efficient, Low Power and Robust Design for Add-Compare-Select UnitsMohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi. 611-614 [doi]
- A Static Low-Power, High-Performance 32-bit Carry Skip AdderKai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis. 615-619 [doi]
- A Novel VLSI Architecture to Implement Region Merging Algorithm for Image SegmentationJ. D. Kranthi Kumar, S. Srinivasan. 620-623 [doi]
- A Threshold Logic Synthesis Tool for RTD CircuitsMaria J. Avedillo, José M. Quintana. 624-627 [doi]