Table of Contents

• Building zynq® accelerators with Vivado® high level synthesisStephen Neuendorffer, Fernando Martinez-Vallina. 1-2 [doi]
• Cross-platform FPGA accelerator development using CoRAM and CONNECTEric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe. 3-4 [doi]
• Harnessing the power of FPGAs using altera's OpenCL compilerDeshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling. 5-6 [doi]
• High-level synthesis with LegUp: a crash course for users and researchersJason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi. 7-8 [doi]
• Improving high level synthesis optimization opportunity through polyhedral transformationsWei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong. 9-18 [doi]
• Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffersEddie Hung, Steven J. E. Wilton. 19-28 [doi]
• Polyhedral-based data reuse optimization for configurable computingLouis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong. 29-38 [doi]
• Faithful single-precision floating-point tangent for FPGAsMartin Langhammer, Bogdan Pasca. 39-42 [doi]
• Accelerating ncRNA homology search with FPGAsNathaniel McVicar, Walter L. Ruzzo, Scott Hauck. 43-52 [doi]
• Accelerating subsequence similarity search based on dynamic time warping distance with FPGAZilong Wang, Sitao Huang, Lanjun Wang, Hao Li, Yu Wang 0002, Huazhong Yang. 53-62 [doi]
• Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platformJungwook Choi, Rob A. Rutenbar. 63-72 [doi]
• Fully-functional FPGA prototype with fine-grain programmable body biasingMasakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi. 73-80 [doi]
• GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extractionBenjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon. 81-90 [doi]
• Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineeringAmir Moradi, David Oswald, Christof Paar, Pawel Swierczynski. 91-100 [doi]
• Sensing nanosecond-scale voltage attacks and natural transients in FPGAsKenneth M. Zick, Meeta Srivastav, Wei Zhang 0044, Matthew French. 101-104 [doi]
• Word-length optimization beyond straight line codeDavid Boland, George A. Constantinides. 105-114 [doi]
• Placement of repair circuits for in-field FPGA repairMichael J. Wirthlin, Joshua E. Jensen, Alex Wilson, William Howes, Shi-Jie Wen, Rick Wong. 115-124 [doi]
• Heracles: a tool for fast RTL-based design space exploration of multicore processorsMichel A. Kinsy, Michael Pellauer, Srinivas Devadas. 125-134 [doi]
• Are FPGAs suffering from the innovator's dilemna?Vaughn Betz, Jason Cong. 135-136 [doi]
• Location, location, location: the role of spatial locality in asymptotic energy minimizationAndré DeHon. 137-146 [doi]
• Architectural enhancements in Stratix V™David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu. 147-156 [doi]
• Minimum energy operation for clustered island-style FPGAsPeter Grossmann, Miriam Leeser, Marvin Onabajo. 157-166 [doi]
• Improving bitstream compression by modifying FPGA architectureSeyyed Ahmad Razavi, Morteza Saheb Zamani. 167-170 [doi]
• Elastic CGRAsYuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu. 171-180 [doi]
• Embedding-based placement of processing element networks on FPGAs for physical model simulationBailey Miller, Frank Vahid, Tony Givargis. 181-190 [doi]
• Area-efficient near-associative memories on FPGAsUdit Dhawan, André DeHon. 191-200 [doi]
• Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizationsJeremy Fowers, Greg Stitt. 201-210 [doi]
• A remote memory access infrastructure for global address space programming models in FPGAsRuediger Willenberg, Paul Chow. 211-220 [doi]
• C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstractionGabriel Weisz, James C. Hoe. 221-230 [doi]
• Architecture support for custom instructions with memory operationsJason Cong, Karthik Gururaj. 231-234 [doi]
• An FPGA based parallel architecture for music melody matchingHao Wang, Jyh-Charn Liu. 235-244 [doi]
• An FPGA memcached applianceSai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala. 245-254 [doi]
• High throughput and programmable online trafficclassifier on FPGADa Tong, Lu Sun, Kiran Kumar Matam, Viktor K. Prasanna. 255-264 [doi]
• FPGA bitstream compression and decompression using LZ and golomb coding (abstract only)Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai. 265 [doi]
• Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)Eric S. Chung, Michael Papamichael. 265 [doi]
• Indirect connection aware attraction for FPGA clustering (abstract only)Meng Yang, Jiarong Tong, A. E. A. Almaini. 265 [doi]
• Hardware implemented real-time operating system (abstract only)Soon Ee Ong, Siaw Chen Lee, Noohul Basheer Zain Ali. 266 [doi]
• A latency-optimized hybrid network for clustering FPGAs (abstract only)Trevor Bunker, Steven Swanson. 266 [doi]
• Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)Anh Tuan Hoang, Takeshi Fujino. 266-267 [doi]
• Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only)Chao Wang, Xi Li, Xuehai Zhou, Jim Martin, Ray C. C. Cheung. 266 [doi]
• FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only)Christos Kyrkou, Christos-Savvas Bouganis, Theocharis Theocharides. 267 [doi]
• Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only)Jing Zhou, Lei Chen, Shuo Wang. 267 [doi]
• High performance architecture for object detection in streamed video (abstract only)Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis. 268 [doi]
• Custom instruction generation and mapping for reconfigurable instruction set processors (abstract only)Chao Wang, Xi Li, Huizhen Zhang, Jinsong Ji, Xuehai Zhou. 268 [doi]
• Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only)Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong. 269 [doi]
• FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only)Andrew Love, Peter Athanas. 269 [doi]
• A novel multithread routing method for FPGAs (abstract only)Chun Zhu, Qiuli Li, Jian Wang, Jinmei Lai. 269 [doi]
• Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only)Sezer Gören, Yusuf Turk, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag. 270 [doi]
• Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only)Vivek Venugopal, Devu Manikantan Shila. 270 [doi]
• A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only)Hasan Baig, Jeong-A. Lee. 270 [doi]
• A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)Qian Zhao, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 271 [doi]
• An FPGA-based transient error simulator for evaluating resilient system designs (abstract only)Chia-Hsiang Chen, Shiming Song, Zhengya Zhang. 271 [doi]
• Acceleration of the long read mapping on a PC-FPGA architecture (abstract only)Peng Chen 0004, Chao Wang, Xi Li, Xuehai Zhou. 271 [doi]
• Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only)Yu Bai, Abigail Fuentes, Mingjie Lin, Mike Riera. 273 [doi]
• Effect of fixed-point arithmetic on deep belief networks (abstract only)Jingfei Jiang, Rongdong Hu, Mikel Luján. 273 [doi]
• A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only)Wenjuan Deng, Yiqun Zhu. 273 [doi]
• AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only)Swapnil Haria, Viktor K. Prasanna. 274 [doi]
• Performance and toolchain of a combined GPU/FPGA desktop (abstract only)Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire. 274 [doi]
• FPGA-based HPC application design for non-experts (abstract only)David Uliana, Krzysztof Kepa, Peter Athanas. 274 [doi]
• Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only)Marc-André Daigneault, Jean-Pierre David. 274-275 [doi]
• Automating resource optimisation in reconfigurable design (abstract only)Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu. 275 [doi]
• Low power FPGA design using post-silicon device aging (abstract only)Sheng Wei, Jason Xin Zheng, Miodrag Potkonjak. 277 [doi]
• Defect recovery in nanodevice-based programmable interconnects (abstract only)Jason Cong, Bingjun Xiao. 277-278 [doi]
• Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only)Oluseyi A. Ayorinde, Benton H. Calhoun. 277 [doi]
• Efficient system-level mapping from streaming applications to FPGAs (abstract only)Jason Cong, Muhuan Huang, Peng Zhang. 277 [doi]
• Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only)Yun Qu, Viktor K. Prasanna. 278 [doi]
• Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)Nick Ni, Yi Peng. 278 [doi]
• A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only)Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt. 278 [doi]
• Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only)Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne. 279 [doi]
• Rectification of advanced microprocessors without changing routing on FPGAs (abstract only)Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita. 279 [doi]