Abstract is missing.
- Fast and effective placement and routing directed high-level synthesis for FPGAsHongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen. 1-10 [doi]
- Optimizing effective interconnect capacitance for FPGA power reductionSafeen Huda, Jason Helge Anderson, Hirotaka Tamura. 11-20 [doi]
- Towards interconnect-adaptive packing for FPGAsJason Luu, Jonathan Rose, Jason Helge Anderson. 21-30 [doi]
- Rent's rule based FPGA packing for routability optimizationWenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu. 31-34 [doi]
- Modular multi-ported SRAM-based memoriesAmeer Abdelhadi, Guy G. F. Lemieux. 35-44 [doi]
- Revisiting and-inverter conesGrace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne. 45-54 [doi]
- Scalable multi-access flash store for big data analyticsSang-Woo Jun, Ming Liu, Kermin Elliott Fleming, Arvind. 55-64 [doi]
- Dynamic voltage & frequency scaling with online slack measurementJoshua M. Levine, Edward A. Stott, Peter Y. K. Cheung. 65-74 [doi]
- Cad and routing architecture for interposer-based multi-FPGA systemsAndré Hahn Pereira, Vaughn Betz. 75-84 [doi]
- Memory block based scan-BIST architecture for application-dependent FPGA testingKeita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue. 85-88 [doi]
- FPGA-based biophysically-meaningful modeling of olivocerebellar neuronsGeorgios Smaragdos, Sebastian Isaza, Martijn F. van Eijk, Ioannis Sourdis, Christos Strydis. 89-98 [doi]
- Square-rich fixed point polynomial evaluation on FPGAsSimin Xu, Suhaib A. Fahmy, Ian Vince McLoughlin. 99-108 [doi]
- Accelerating frequent item counting with FPGAYuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang, Rong Luo, Huazhong Yang. 109-112 [doi]
- A power side-channel-based digital to analog converterfor Xilinx FPGAsBrad L. Hutchings, Joshua S. Monson, Danny Savory, Jared Keeley. 113-116 [doi]
- Soft vector processors with streaming pipelinesAaron Severance, Joe Edwards, Hossein Omidian, Guy Lemieux. 117-126 [doi]
- MORP: makespan optimization for processors with an embedded reconfigurable fabricArtjom Grudnitsky, Lars Bauer, Jörg Henkel. 127-136 [doi]
- OmpSs@Zynq all-programmable SoC ecosystemAntonio Filgueras, Eduard Gil, Daniel Jiménez-González, Carlos Alvarez, Xavier Martorell, Jan Langer, Juanjo Noguera, Kees A. Vissers. 137-146 [doi]
- A FPGA prototype design emphasis on low power techniqueHanyang Xu, Jian Wang, Meilai Jin. 147-150 [doi]
- Hardware acceleration of database operationsJared Casper, Kunle Olukotun. 151-160 [doi]
- A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAsRichard Dorrance, Fengbo Ren, Dejan Markovic. 161-170 [doi]
- Binary stochastic implementation of digital logicYanzi Zhu, Peiran Suo, Kia Bazargan. 171-180 [doi]
- Accelerating parameter estimation for multivariate self-exciting point processesCe Guo, Wayne Luk. 181-184 [doi]
- Energy-efficient multiplier-less discrete convolver through probabilistic domain transformationMohammed Alawad, Bai Yu, Ronald F. DeMara, Mingjie Lin. 185-188 [doi]
- Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimizationAndré DeHon. 189-198 [doi]
- Theory and algorithm for generalized memory partitioning in high-level synthesisYuxin Wang, Peng Li, Jason Cong. 199-208 [doi]
- Using high-level synthesis and formal analysis to predict and preempt attacks on industrial control systemsLee W. Lerner, Zane R. Franklin, William T. Baumann, Cameron D. Patterson. 209-212 [doi]
- Combining computation and communication optimizations in system synthesis for streaming applicationsJason Cong, Muhuan Huang, Peng Zhang. 213-222 [doi]
- Quantifying the cost and benefit of latency insensitive communication on FPGAsKevin E. Murray, Vaughn Betz. 223-232 [doi]
- MPack: global memory optimization for stream applications in high-level synthesisJasmina Vasiljevic, Paul Chow. 233-236 [doi]
- A soft error vulnerability analysis framework for Xilinx FPGAsAitzan Sari, Dimitris Agiakatsikas, Mihalis Psarakis. 237-240 [doi]
- A new basic logic structure for data-path computation (abstract only)Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Giovanni De Micheli. 241 [doi]
- FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only)Monther Abusultan, Sunil P. Khatri. 241 [doi]
- A configurable mapreduce accelerator for multi-core FPGAs (abstract only)Christoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris. 241 [doi]
- A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only)Ka Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young. 242 [doi]
- Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only)Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang. 242 [doi]
- A methodology for identifying and placing heterogeneous cluster groups based on placement proximity data (abstract only)Farnaz Gharibian, Lesley Shannon, Peter Jamieson. 242 [doi]
- Hierarchical library-based power estimator for versatile FPGAs (abstract only)Hao Liang, Yi-Chung Chen, Wei Zhang, Hai Li. 243 [doi]
- On hybrid memory allocation for FPGA behavioral synthesis (abstract only)Qian Zhang, Chenfei Ma, Qiang Xu. 245 [doi]
- Pushing the performance boundary of linear projection designs through device specific optimisations (abstract only)Rui Policarpo Duarte, Christos-Savvas Bouganis. 245 [doi]
- Transformations for throughput optimization in high-level synthesis (abstract only)Peng Li, Louis-Noël Pouchet, Deming Chen, Jason Cong. 245 [doi]
- Accelerating massive short reads mapping for next generation sequencing (abstract only)Chunming Zhang, Wen Tang, Guangming Tan. 246 [doi]
- Optimally mitigating BTI-induced FPGA device aging with discriminative voltage scaling (abstract only)Bai Yu, Mohammed Alawad, Mingjie Lin. 246 [doi]
- Application specific processor with high level synthesized instructions (abstract only)Viktor Pus, Pavel Benácek. 246 [doi]
- A power-efficient adaptive heapsort for fpga-based image coding application (abstract only)Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado. 247 [doi]
- Design, implementation and security analysis of hardware trojan threats in FPGA (abstract only)Devu Manikantan Shila, Vivek Venugopal. 247 [doi]
- Big data genome sequencing on Zynq based clusters (abstract only)Chao Wang, Xi Li, Xuehai Zhou, Yunji Chen, Ray C. C. Cheung. 247 [doi]
- Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only)Chao Wang, Xi Li, Xuehai Zhou, Yunji Chen, Koen Bertels. 248 [doi]
- Redefining the role of FPGAs in the next generation avionic systems (abstract only)Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser, Benjamin Nakache, Maurice Nakache. 248 [doi]
- BMP: a fast B*-tree based modular placer for FPGAs (abstract only)Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai Li. 248 [doi]
- Control signal aware slice-level window based legalization method for FPGA placement (abstract only)Yu Wang, Donghoon Yeo, Muhammad Sohail, Hyunchul Shin. 249 [doi]
- Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only)Ahmad Alzahrani, Ronald F. DeMara. 251 [doi]
- Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only)Qingshan Tang, Matthieu Tuna, Habib Mehrez. 251 [doi]
- 1K manycore FPGA shared memory architecture for SOC (abstract only)Yosi Ben-Asher, Jacob Gendel, Gadi Haber, Oren Segal, Yousef Shajrawi. 251 [doi]
- APMC: advanced pattern based memory controller (abstract only)Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Santhosh Kumar Rethinagiri. 252 [doi]
- Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only)Roshan Silwal, Mohammed Y. Niamat. 252 [doi]
- Novel FPGA clock network with low latency and skew (abstract only)Lei Li, Jian Wang, Jinmei Lai. 252 [doi]
- On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only)Sen Ma, David L. Andrews. 253 [doi]
- Producing high-quality real-time HDR video system with FPGA (abstract only)Tao Ai, Mir Adnan Ali, J. Gregory Steffan, Kalin Ovtcharov, Sarmad Zulfiqar, Steve Mann. 253 [doi]
- xDEFENSE: an extended DEFENSE for mitigating next generation intrusions (abstract only)James Lamberti, Devu Manikantan Shila, Vivek Venugopal. 253 [doi]
- Coordinating routing resources for hex pips test in island-style FPGAs (abstract only)Fan Zhang, Lei Chen, Wenyao Xu, Yuanfu Zhao, Zhiping Wen. 254 [doi]
- Pipelining FPPGA-based defect detction in FPDs (abstract only)Lin Meng, Keisuke Matsuyama, Naoto Nojiri, Tomonori Izumi, Katsuhiro Yamazaki. 254 [doi]
- Methodology to generate multi-dimensional systolic arrays for FPGAs using openCL (abstract only)Nick Ni. 255 [doi]
- Implementing FPGA-based energy-efficient dense optical flow computation with high portability in C (abstract only)Zhibin Wang, Wenmin Yang, Jin Yu, ZhiLei Chai. 255 [doi]
- EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only)Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong, Tao Wang. 255 [doi]
- Improving the security and the scalability of the AES algorithm (abstract only)Alessandro Antonio Nacci, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 256 [doi]
- Power estimation tool for system on programmable chip based platforms (abstract only)Santhosh Kumar Rethinagiri, Oscar Palomar, Adrián Cristal, Osman S. Unsal. 256 [doi]
- Using DSP blocks to compute CRC hash in FPGA (abstract only)Viktor Pus, Lukas Kekely, Tomás Závodník. 256 [doi]
- An automatic netlist and floorplanning approach to improve the MTTR of scrubbing techniques (abstract only)Bernhard Schmidt, Daniel Ziener, Jürgen Teich. 257 [doi]
- Exploring duty cycle distortions along signal paths in FPGAs (abstract only)Matthias Hinkfoth, Ralf Joost, Ralf Salomon. 257 [doi]