Abstract is missing.
- An FPGA-based Transverse Multibunch Feedback System for Diamond Light SourceIsa Uzun, Mark Heron, Alun Morgan, Guenther Rehm. 1-4 [doi]
- Control Techniques for Coupling a Coarse-Grain Reconfigurable Array with a Generic RISC CoreFabio Garzia, Waqar Hussain, Jari Nurmi. 5-9 [doi]
- Exploiting Dynamic Reconfiguration for FPGA Based Network Intrusion Detection SystemsSalvatore Pontarelli, Claudio Greco, Enrico Nobile, Simone Teofili, Giuseppe Bianchi. 10-14 [doi]
- A Scalable, High-Performance Motion Estimation Application for a Weakly-Programmable FPGA ArchitectureHenning Sahlbach, Sean Whitty, Oliver Bende, Rolf Ernst. 15-18 [doi]
- Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save ArithmeticAmit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. 19-24 [doi]
- An FPGA Based Hybrid Processor Emulation PlatformQigang Wang, Rolf Kassa, Wenbo Shen, Nelson Ijih, Bhushan Chitlur, Michael Konow, Dong Liu, Arthur Sheiman, Prabhat Gupta. 25-30 [doi]
- Parallelizing Simulated Annealing-Based Placement Using GPGPUAlexander Choong, Rami Beidas, Jianwen Zhu. 31-34 [doi]
- Efficiently Generating FPGA Configurations through a Stack MachineFatma Abouelella, Karel Bruneel, Dirk Stroobandt. 35-39 [doi]
- Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGASangKyun Yun, KyuHee Lee. 40-43 [doi]
- A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression MatchingFrancesco Bruschi, Marco Paolieri, Vincenzo Rana. 44-49 [doi]
- Automation Framework for Large-Scale Regular Expression Matching on FPGAThilan Ganegedara, Yi-Hua E. Yang, Viktor K. Prasanna. 50-55 [doi]
- Real-Time Classification of Multimedia Traffic Using FPGAWeirong Jiang, Maya Gokhale. 56-63 [doi]
- Parallel Hardware Implementation of Connected Component Tree ComputationPetr Matas, Eva Dokladalova, Mohamed Akil, Vjaceslav Georgiev, Martin Poupa. 64-69 [doi]
- Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCsAndrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva. 70-76 [doi]
- FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift RegistersDavid B. Thomas, Wayne Luk. 77-82 [doi]
- High-Performance Integer Factoring with Reconfigurable DevicesRalf Zimmermann, Tim Güneysu, Christof Paar. 83-88 [doi]
- Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGAChalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides. 89-94 [doi]
- Advanced Multithreading Architecture with Hardware Based SchedulingYe Lu, Sakir Sezer, John V. McCanny. 95-100 [doi]
- Thermal Gradient Aware Clock Skew Scheduling for FPGAsSungmin Bae, Narayanan Vijaykrishnan. 101-106 [doi]
- A Reconfigurable Computing Scheduler Optimized for Multicore SystemsPhilip Garcia, Kyle Rupnow, Katherine Compton. 107-112 [doi]
- An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform TradeoffsBrian Leung, Chih-Hung Wu, Seda Ogrenci Memik, Sanjay Mehrotra. 113-118 [doi]
- GPU Versus FPGA for High Productivity ComputingDavid Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung. 119-124 [doi]
- Parallelizing FPGA Technology Mapping Using Graphics Processing Units (GPUs)Doris Chen, Deshanand Singh. 125-132 [doi]
- Breaking Elliptic Curve Cryptosystems Using Reconfigurable HardwareJunfeng Fan, Daniel V. Bailey, Lejla Batina, Tim Güneysu, Christof Paar, Ingrid Verbauwhede. 133-138 [doi]
- Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor ArchitecturesLyonel Barthe, Pascal Benoit, Lionel Torres. 139-144 [doi]
- Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password CrackingKostas Theocharoulis, Ioannis Papaefstathiou, Charalampos Manifavas. 145-150 [doi]
- Detecting Patterns in Various Size and Angle Using FPGAMasayuki Suzuki, Yoshifumi Tanida, Tsutomu Maruyama. 151-154 [doi]
- Real-Time Processing of Contrast Limited Adaptive Histogram Equalization on FPGAKentaro Kokufuta, Tsutomu Maruyama. 155-158 [doi]
- Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoCHung-Manh Pham, Sébastien Pillement, Didier Demigny. 159-162 [doi]
- Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading EngineStephen Wray, Wayne Luk, Peter Pietzuch. 163-166 [doi]
- Sum of Absolute Difference Implementations for Image Processing on FPGAsHiroaki Niitsuma, Tsutomu Maruyama. 167-170 [doi]
- Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra PredictionYusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu. 171-174 [doi]
- Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR FiltersAmir Hossein Gholamipour, Fadi J. Kurdahi, Ahmed M. Eltawil, Mazen A. R. Saghir. 175-178 [doi]
- Secure Protocol Implementation for Remote Bitstream Update Preventing Replay Attacks on FPGAFlorian Devic, Lionel Torres, Benoît Badrignans. 179-182 [doi]
- Online Routing Fault Detection for Reconfigurable NoCCedric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache. 183-186 [doi]
- Self-Aware Adaptation in FPGA-based SystemsF. Sironi, M. Triverio, Henry Hoffmann, Martina Maggio, Marco D. Santambrogio. 187-192 [doi]
- Self-Test and Adaptation for Random Variations in ReliabilityKenneth M. Zick, John P. Hayes. 193-198 [doi]
- Memory System for a Dynamically Adaptable Pixel Stream ArchitectureNicolas Ngan, Geoffroy Marpeaux, Eva Dokladalova, Mohamed Akil, François Contou-Carrère. 199-204 [doi]
- Test Compression for Dynamically Reconfigurable ProcessorsHiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro Furuta. 205-210 [doi]
- A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog BlocksWen-Hui Fu, Jun Jiang, Xi Qin, Ting Yi, Zhiliang Hong. 211-216 [doi]
- Customized Exposed Datapath Soft-Core Design Flow with Compiler SupportOtto Esko, Pekka Jääskeläinen, Pablo Huerta, Carlos S. de La Lama, Jarmo Takala, José Ignacio Martínez. 217-222 [doi]
- A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and BarrierHeiner Giefers, Marco Platzner. 223-228 [doi]
- Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of RoutersLeandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner. 229-233 [doi]
- A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAsAndreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch. 234-239 [doi]
- Design and Implementation of an Object-Oriented Framework for Dynamic Partial ReconfigurationNorbert Abel. 240-243 [doi]
- Erlang Inspired HardwarePaulo Ferreira, João Canas Ferreira, José Carlos Alves. 244-246 [doi]
- IP Based Configurable SIMD Massively Parallel SoCMouna Baklouti, Mohamed Abid, Philippe Marquet, Jean-Luc Dekeyser. 247-250 [doi]
- FPGA Based Engines for Genetic and Memetic AlgorithmsPedro V. Santos, José C. Alves. 251-254 [doi]
- Proof-Carrying Hardware: Runtime Formal Verification for Secure Dynamic ReconfigurationStephanie Drzevitzky. 255-258 [doi]
- Robust FPGA Design under VariationsAkhilesh Kumar, Mohab Anis. 259-262 [doi]
- On Identifying Segments of Traces for Dynamic CompilationJoão Bispo, João M. P. Cardoso. 263-266 [doi]
- On Identifying Patterns in Code Repositories to Assist the Generation of Hardware TemplatesAdriano K. Sanches, João M. P. Cardoso. 267-270 [doi]
- Software Managed Distributed Memories in MPPAsRobin Panda, Jimmy Xu, Scott Hauck. 271-278 [doi]
- Design and Implementation of Real-Time Transactional MemoryMartin Schoeberl, Peter Hilber. 279-284 [doi]
- Rapid Application Development on Multi-processor Reconfigurable SystemsLinfeng Ye, Jean-Philippe Diguet, Guy Gogniat. 285-290 [doi]
- Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAsSyed Zahid Ahmed, Gilles Sassatelli, Lionel Torres, Laurent Rouge. 291-297 [doi]
- First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM CellsMasahiro Koga, Masahiro Iida, Motoki Amagasaki, Yoshinobu Ichida, Mitsuro Saji, Jun Iida, Toshinori Sueyoshi. 298-303 [doi]
- COGRE: A Configuration Memory Reduced Reconfigurable Logic Cell Architecture for Area MinimizationYasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. 304-309 [doi]
- PrEsto: An FPGA-accelerated Power Estimation Methodology for Complex SystemsDam Sunwoo, Gene Y. Wu, Nikhil A. Patil, Derek Chiou. 310-317 [doi]
- Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry ChainsThomas B. Preußer, Rainer G. Spallek. 318-325 [doi]
- Rapid Prototyping of Radiation-Tolerant Embedded Systems on FPGAF. Restrepo-Calle, A. Martinez-Alvarez, F. R. Palomo, Hipólito Guzmán-Miranda, M. A. Aguirre, S. Cuenca Asensi. 326-331 [doi]
- A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAsMarcus Ritt, Carlos Arthur Lang Lisbôa, Luigi Carro, Cristiano Lazzari. 332-335 [doi]
- Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating TechniqueAntonin Hermanek, Michal Kunes, Milan Tichý. 336-339 [doi]
- Generation of Deterministic MCU/FPGA Hybrid Systems from UML ActivitiesRuediger Willenberg, Zamira Daw, Christian Englert, Marcus Vetter. 340-345 [doi]
- Real-Time Fault Detection and Diagnostics Using FPGA-based ArchitecturesNathan Naber, Thomas Getz, Yong Kim, James Petrosky. 346-351 [doi]
- A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable SystemsKrzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada. 352-355 [doi]
- NIFD: Non-intrusive FPGA Debugger -- Debugging FPGA Threads for Rapid HW/SW Systems PrototypingHari Angepat, Gage Eads, Christopher Craik, Derek Chiou. 356-359 [doi]
- Exploration of Short Reads Genome Mapping in HardwareEdward Fernandez, Walid Najjar, Elena Yavorska Harris, Stefano Lonardi. 360-363 [doi]
- Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic OptionsAnson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk. 364-367 [doi]
- Ultra-low-Power Ultra-fast Hybrid CNEMS-CMOS FPGAVijay K. Sirigir, Khawla Alzoubi, Daniel G. Saab, Fatih Kocan, Massood Tabib-Azar. 368-373 [doi]
- High Density Asynchronous LUT Based on Non-volatile MRAM TechnologySumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer. 374-379 [doi]
- Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable ArraysBrian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck. 380-387 [doi]
- Design and FPGA Implementation of a 2nd Order Adaptive Delta Sigma Modulator with One Bit QuantizationShahrukh Athar, Muhammad Ali Siddiqi, Shahid Masud. 388-393 [doi]
- Decision Forest: A Scalable Architecture for Flexible Flow Matching on FPGAWeirong Jiang, Viktor K. Prasanna, Norio Yamagaki. 394-399 [doi]
- FPGA Implementations of the Round Two SHA-3 CandidatesBrian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Máire O Neill, William P. Marnane. 400-407 [doi]
- ERCBench: An Open-Source Benchmark Suite for Embedded and Reconfigurable ComputingDaniel W. Chang, Christipher D. Jenkins, Philip C. Garcia, Syed Z. Gilani, Paula Aguilera, Aishwarya Nagarajan, Michael J. Anderson, Matthew A. Kenny, Sean M. Bauer, Michael J. Schulte, Katherine Compton. 408-413 [doi]
- ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAsKris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster. 414-421 [doi]
- Pipelined FPGA AddersFlorent de Dinechin, Hong Diep Nguyen, Bogdan Pasca. 422-427 [doi]
- Degradation Analysis and Mitigation in FPGAsEdward A. Stott, Justin S. Wong, Peter Y. K. Cheung. 428-433 [doi]
- A Karatsuba-Based Montgomery MultiplierGary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Leong. 434-437 [doi]
- Using Hard Macros to Reduce FPGA Compilation TimeChristopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin. 438-441 [doi]
- SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencingKristian Stevens, Henry Chen, Terry Filiba, Peter McMahon, Yun S. Song. 442-447 [doi]
- Reconfigurable Systems for the Zuker and Predator Algorithms for Secondary Structure Prediction of Genetic DataMiltiadis Smerdis, Panagiotis Dagritzikos, Grigorios Chrysos, Euripides Sotiriades, Apostolos Dollas. 448-451 [doi]
- LavA: An Open Platform for Rapid Prototyping of MPSoCsMatthias Meier, Michael Engel, Matthias Steinkamp, Olaf Spinczyk. 452-457 [doi]
- OpenRCL: Low-Power High-Performance Computing with Reconfigurable DevicesMingjie Lin, Ilia A. Lebedev, John Wawrzynek. 458-463 [doi]
- Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGAGhizlane Lhairech-Lebreton, Philippe Coussy, Eric Martin. 464-468 [doi]
- A Comparison of Hardware Acceleration Interfaces in a Customizable Soft Core ProcessorGerald Hempel, Christian Hochberger, Andreas Koch. 469-474 [doi]
- A Flexible Compute and Memory Infrastructure for High-Level Language to Hardware CompilationHagen Gädke-Lütjens, Benjamin Thielmann, Andreas Koch. 475-482 [doi]
- Early Prediction of Hardware Complexity in HLL-to-HDL TranslationAlessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo. 483-488 [doi]
- An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point MultiplierMalte Baesler, Sven-Ole Voigt, Thomas Teufel. 489-495 [doi]
- Efficient FPGA Modular Multiplication and Exponentiation Architectures Using Digit Serial ComputationGustavo Sutter, Jean-Pierre Deschamps, José Luis Imaña. 496-501 [doi]
- Accurate Time-to-Digital Converter Based on Xilinx s Digital Clock ManagersAngel Quiros Olozabal, Ma de los Angeles Cifredo Chacon, Jose Maria Guerrero-Rodriguez. 502-507 [doi]
- Dynamically Reconfigurable Vision-Chip ArchitectureMaki Yasuda, Minoru Watanabe. 508-512 [doi]
- Flexible and Modular Support for Timing Functions in High Performance Networking AccelerationChristopher E. Neely, Gordon J. Brebner, Weijia Shang. 513-518 [doi]
- FPGA Based Network Traffic Analysis Using Traffic Dispersion PatternsFaisal Khan, Maya Gokhale, Chen-Nee Chuah. 519-524 [doi]
- Reconfigurable Hardware for Power-over-Fiber ApplicationsMichael Dreschmann, Michael Hübner, Moritz Roger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold. 525-531 [doi]
- Efficient FPGA Resynthesis Using Precomputed LUT StructuresAndrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu. 532-537 [doi]
- Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and SynthesisAdam Arnesen, Kevin Ellsworth, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent E. Nelson, Michael Rice, Michael J. Wirthlin. 538-543 [doi]
- Finding System-Level Information and Analyzing Its Correlation to FPGA PlacementFarnaz Gharibian, Lesley Shannon, Peter Jamieson. 544-549 [doi]
- FPGA-accelerated Attractor Computation of Scale Free Gene Regulatory NetworksRicardo S. Ferreira, Julio C. Goldner Vendramini. 550-555 [doi]
- A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train AnalysisBo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon. 556-561 [doi]
- An FPGA-based High-Speed, Low-Latency Processing System for High-Energy PhysicsStefan Kirsch, Felix Rettig, Dirk Hutter, Jan de Cuveland, Venelin Angelov, Volker Lindenstruth. 562-567 [doi]
- FEM: A Step Towards a Common Memory Layout for FPGA Based AcceleratorsMuhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 568-573 [doi]
- Multiplicative Square Root Algorithms for FPGAsFlorent de Dinechin, Mioara Joldes, Bogdan Pasca, Guillaume Revy. 574-577 [doi]
- A Compact Transactional Memory Multiprocessor System on FPGAMatteo Pusceddu, Simone Ceccolini, Gianluca Palermo, Donatella Sciuto, Antonino Tumeo. 578-581 [doi]
- Field Programmable Gate Array Implementation of Parts-Based Object Detection for Real Time Video ApplicationsDeborah Goshorn, Junguk Cho, Ryan Kastner, Shahnam Mirzaei. 582-587 [doi]
- General Purpose Computing with Reconfigurable AccelerationAnthony Brandon, Ioannis Sourdis, Georgi Nedeltchev Gaydadjiev. 588-591 [doi]
- MalCoBox: Designing a 10 Gb/s Malware Collection Honeypot Using Reconfigurable TechnologySascha Mühlbach, Martin Brunner, Christopher Roblee, Andreas Koch. 592-595 [doi]
- Short-Circuits on FPGAs Caused by Partial Runtime ReconfigurationChristian Beckhoff, Dirk Koch, Jim Torresen. 596-601 [doi]
- Dynamic Reconfiguration Optimisation with Streaming Data DecompressionAtukem Nabina, José L. Núñez-Yáñez. 602-607 [doi]
- Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA VideoKosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto. 608-611 [doi]