Abstract is missing.
- Recent advances in die stacking and 3D FPGAArif Rahman. 1 [doi]
- Reconfigurable chip advantage compared with GPGPU from the compiler perspectiveKazutoshi Wakabayashi. 2 [doi]
- Why Put FPGAs in your CPU socket?Paul Chow. 3 [doi]
- Accelerating validation of time-triggered automotive systems on FPGAsShanker Shreejith, Suhaib A. Fahmy, Martin Lukasiewycz. 4-11 [doi]
- Exploiting partially defective LUTs: Why you don't need perfect fabricationAndré DeHon, Nikil Mehta. 12-19 [doi]
- Maximum flow algorithms for maximum observability during FPGA debugEddie Hung, Al-Shahna Jamal, Steven J. E. Wilton. 20-27 [doi]
- The architecture and placement algorithm for a uni-directional routing based 3D FPGAJunsong Hou, Heng Yu, Yajun Ha, Xin Liu. 28-33 [doi]
- COFFE: Fully-automated transistor sizing for FPGAsCharles Chiasson, Vaughn Betz. 34-41 [doi]
- A case for hardened multiplexers in FPGAsS. Alexander Chin, Jason Helge Anderson. 42-49 [doi]
- Debugging processors with advanced features by reprogramming LUTs on FPGASatoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita. 50-57 [doi]
- Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilitiesRoberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini. 58-65 [doi]
- Accelerating iterative algorithms with asynchronous accumulative updates on FPGAsDeepak Unnikrishnan, Sandesh Gubbi Virupaksha, Lekshmi Krishnan, Lixin Gao, Russell Tessier. 66-73 [doi]
- High throughput, tree automata based XML processing using FPGAsReetinder Sidhu. 74-81 [doi]
- Transparent FPGA based device for SQL DDoS mitigationKarthikeyan Pandiyarajan, Srijith Haridas, Kuruvilla Varghese. 82-89 [doi]
- Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systemsTim Pifer, David Schwartz, Roman Lysecky, Chungman Seo, Bernard P. Zeigler. 98-105 [doi]
- Optimizing time and space multiplexed computation in a dynamically reconfigurable processorTakao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima. 106-111 [doi]
- SOAP: Structural optimization of arithmetic expressions for high-level synthesisXitong Gao, Samuel Bayliss, George A. Constantinides. 112-119 [doi]
- Making domain-specific hardware synthesis tools cost-efficientNithin George, David Novo, Tiark Rompf, Martin Odersky, Paolo Ienne. 120-127 [doi]
- System-level FPGA device driver with high-level synthesis supportKizheppatt Vipin, Shanker Shreejith, Dulitha Gunasekera, Suhaib A. Fahmy, Nachiket Kapre. 128-135 [doi]
- Bitwidth-optimized hardware accelerators with software fallbackAna Klimovic, Jason Helge Anderson. 136-143 [doi]
- A low latency kernel recursive least squares processor using FPGA technologyYeyong Pang, Shaojun Wang, Yu Peng, Nicholas J. Fraser, Philip H. W. Leong. 144-151 [doi]
- Implementation of high performance hardware architecture of OpenSURF algorithm on FPGAXitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang. 152-159 [doi]
- TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAsSebastian Kutzner, Axel Poschmann, Marc Stöttinger. 160-167 [doi]
- Real-time and low power embedded ℓ1-optimization solver designZhi Ping Ang, Akash Kumar. 168-175 [doi]
- Efficient execution of augmented reality applications on mobile programmable acceleratorsJason Jong Kyu Park, Yongjun Park, Scott A. Mahlke. 176-183 [doi]
- An OpenCL optimizing compiler for reconfigurable processorsJeongho Nah, Jun Lee, Hongjune Kim, Jinseok Lee, Seok Joong Hwang, Donghoon Yoo, Jaejin Lee. 184-191 [doi]
- Real-time ray tracing on coarse-grained reconfigurable processorJaedon Lee, Youngsam Shin, Won-Jong Lee, Soojung Ryu, Jeongwook Kim. 192-197 [doi]
- Mobile GPU shader processor based on non-blocking Coarse Grained Reconfigurable Arrays architectureKwontaek Kwon, Sungjin Son, Jeongsoo Park, Jeongae Park, Sangoak Woo, Seokyoon Jung, Soojung Ryu. 198-205 [doi]
- Acceleration of real-time Proximity Query for dynamic active constraintsThomas C. P. Chau, Ka Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk. 206-213 [doi]
- Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clustersXinyu Niu, José Gabriel F. Coutinho, Yu Wang 0002, Wayne Luk. 214-221 [doi]
- FlexGrip: A soft GPGPU for FPGAsKevin Andryc, Murtaza Merchant, Russell Tessier. 230-237 [doi]
- Maximizing speed and density of tiled FPGA overlays via partitioningCharles Eric LaForest, J. Gregory Steffan. 238-245 [doi]
- Improving clock-rate of hard-macro designsChristopher Lavin, Brent E. Nelson, Brad L. Hutchings. 246-253 [doi]
- Exploiting stochastic delay variability on FPGAs with adaptive partial reroutingZhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung. 254-261 [doi]
- Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board designDaniel P. Seemuth, Katherine Morrow. 262-269 [doi]
- From software threads to parallel hardware in high-level synthesis for FPGAsJongsok Choi, Stephen Dean Brown, Jason Helge Anderson. 270-277 [doi]
- StML: Bridging the gap between FPGA design and HDL circuit descriptionDustin Peterson, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel. 278-285 [doi]
- Derivation of efficient FSM from loop nestsTomofumi Yuki, Antoine Morvan, Steven Derrien. 286-293 [doi]
- An automated flow for the High Level Synthesis of coarse grained parallel applicationsVito Giovanni Castellana, Fabrizio Ferrandi. 294-301 [doi]
- A high-throughput FPGA architecture for parallel connected components analysis based on label reuseMichael Klaiber, Donald G. Bailey, Silvia Ahmed, Yousef Baroud, Sven Simon. 302-305 [doi]
- Teaching FPGA securityLilian Bossuet. 306-309 [doi]
- Fast Boolean matching based on NPN classificationZheng Huang, Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko. 310-313 [doi]
- Multi-personality partitioning for heterogeneous systemsAnthony E. Gregerson, Aman Chadha, Katherine Morrow. 314-317 [doi]
- A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGAHenry Block, Tsutomu Maruyama. 318-321 [doi]
- Application-specific customisation of market data feed arbitrationStewart Denholm, Hiroaki Inoue, Takashi Takenaka, Wayne Luk. 322-325 [doi]
- A connection-based router for FPGAsElias Vansteenkiste, Karel Bruneel, Dirk Stroobandt. 326-329 [doi]
- Flexible hierarchy ray tracing on FPGAsSam Collinson, Oliver Sinnen. 330-333 [doi]
- Design and optimization of heterogeneous tree-based FPGA using 3D technologyVinod Pangracious, Zied Marrakchi, Habib Mehrez. 334-337 [doi]
- NFA reduction for regular expressions matching using FPGAVlastimil Kosar, Martin Zádník, Jan Korenek. 338-341 [doi]
- Runtime hardware/software task transition scheduling for data-adaptable embedded systemsNathan Sandoval, Casey Mackin, Sean Whitsitt, Roman L. Lysecky, Jonathan Sprinkle. 342-345 [doi]
- A speculative gather system for Cool Mega-ArrayRie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano. 346-349 [doi]
- An acceleration method of short read mapping using FPGAYoko Sogabe, Tsutomu Maruyama. 350-353 [doi]
- Quantum FPGA architecture designJialin Chen, Lingli Wang, Bin Wang. 354-357 [doi]
- Real-time high-quality stereo vision system in FPGAWen Qiang Wang, Jing Yan, Ning-Yi Xu, Yu Wang, Feng-hsiung Hsu. 358-361 [doi]
- High-level synthesis of dynamic data structures: A case study using Vivado HLSFelix Winterstein, Samuel Bayliss, George A. Constantinides. 362-365 [doi]
- Datapath fault tolerance for parallel acceleratorsJames J. Davis, Peter Y. K. Cheung. 366-369 [doi]
- Hardware acceleration of biomedical models with OpenCMISS and CellMLTing Yu, Chris Bradley, Oliver Sinnen. 370-373 [doi]
- sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interfaceYongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung. 374-377 [doi]
- A 66.1 Gbps single-pipeline AES on FPGAQiang Liu, Zhenyu Xu, Ye Yuan. 378-381 [doi]
- Partially reconfigurable flux calculation scheme in advection term computationMohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita, Hideharu Amano. 382-385 [doi]
- FPGA-accelerated key search for cold-boot attacks against AESHeinrich Riebler, Tobias Kenter, Christoph Sorge, Christian Plessl. 386-389 [doi]
- A low power reconfigurable accelerator using a back-gate bias control techniqueHongliang Su, Weihan Wang, Kuniaki Kitamori, Hideharu Amano. 390-393 [doi]
- Adaptive compression for instruction code of Coarse Grained Reconfigurable ArchitecturesMoo-Kyoung Chung, Jun Kyoung Kim, Yeon Gon Cho, Soojung Ryu. 394-397 [doi]
- A non-intrusive portable fault injection framework to assess reliability of FPGA-based designsElyas Abolhassani Ghazaani, Zana Ghaderi, Seyed Ghassem Miremadi. 398-401 [doi]
- High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficientsRui Jia, Fei Wang, Rui Chen, Xin Gang Wang, Delong Shang, Hai-Gang Yang. 402-405 [doi]
- Color configuration method for an optically reconfigurable gate arrayTakumi Fujimori, Minoru Watanabe. 406-409 [doi]
- Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisationDavid Boland, George A. Constantinides. 410-413 [doi]
- EasyPR - An easy usable open-source PR systemDirk Koch, Christian Beckhoff, Alexander Wold, Jim Torresen. 414-417 [doi]
- A hardware implementation of Bag of Words and Simhash for image recognitionShengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang. 418-421 [doi]
- An FPGA-cluster-accelerated match engine for content-based image retrievalChen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang. 422-425 [doi]
- Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture designHung-Lin Chao, Chun-Yang Peng, Cheng-Chien Wu, Ken-Shin Huang, Chun-Hsien Lu, Jih-Sheng Shen, Pao-Ann Hsiung. 426-429 [doi]
- A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burstHiroki Nakahara, Kazumasa Iwai, Hiroyuki Nakanishi. 430-433 [doi]
- A defect-tolerant cluster in a mesh SRAM-based FPGAArwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi. 434-437 [doi]
- Reconfigurable filtered acceleration of short read alignmentJames Arram, Wayne Luk, Peiyong Jiang. 438-441 [doi]
- Efficient methods for out-of-order load/store execution for high-performance soft processorsHenry Wong, Vaughn Betz, Jonathan Rose. 442-445 [doi]
- Semantics-directed machine architecture in ReWireAdam M. Procter, William L. Harrison, Ian Graves, Michela Becchi, Gerard Allwein. 446-449 [doi]
- ZCluster: A Zynq-based Hadoop clusterZhongduo Lin, Paul Chow. 450-453 [doi]
- An open-source SATA core for Virtex-4 FPGAsCory Gorman, Paul Siqueira, Russell Tessier. 454-457 [doi]
- Direct virtual memory access from FPGA for high-productivity heterogeneous computingHo-Cheung Ng, Yuk-Ming Choi, Hayden Kwok-Hay So. 458-461 [doi]
- Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injectionJohannes Maximilian Kuhn, Thomas Schweizer, Dustin Peterson, Tommy Kuhn, Wolfgang Rosenstiel. 462-465 [doi]
- Task level pipelining with PEACH2: An FPGA switching fabric for high performance computingTakaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku. 466-469 [doi]
- Enhancing communication on automotive networks using data layer extensionsShanker Shreejith, Suhaib A. Fahmy. 470-473 [doi]
- A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluationTakeshi Ohkawa, Takashi Yokota, Kanemitsu Ootsu. 474-477 [doi]
- Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computingWill X. Y. Li, Shridhar Chaudhary, Ray C. C. Cheung, Takeshi Matsumoto, Masahiro Fujita. 478-479 [doi]
- Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic arrayPeng Chen 0004, Chao Wang, Xi Li, Xuehai Zhou. 480-481 [doi]
- Implementation of a highly scalable blokus duo solver on FPGAChester Liu. 482-485 [doi]
- From C to Blokus Duo with LegUp high-level synthesisJiu Cheng Cai, Ruolong Lian, MengYao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson. 486-489 [doi]
- The Liquid Metal Blokus Duo DesignErik R. Altman, Joshua S. Auerbach, David F. Bacon, Ioana Baldini, Perry Cheng, Stephen J. Fink, Rodric M. Rabbah. 490-493 [doi]
- FPGA Blokus Duo Solver using a massively parallel architectureTakashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe. 494-497 [doi]
- Artificial intelligence of Blokus Duo on FPGA using Cyber Work BenchNaru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Yuki Katuta, Takushi Mitsuichi, Hideharu Amano. 498-501 [doi]
- An FPGA-based specific processor for Blokus DuoJavier Olivito, Carlos González, Javier Resano. 502-505 [doi]
- An implementation of Blokus Duo player on FPGAAkira Kojima. 506-509 [doi]
- Correction to "Graph Minor Approach for Application Mapping on CGRAs"Liang Chen, Tulika Mitra. 510 [doi]