Abstract is missing.
- Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistorsJanusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören. [doi]
- Keynote 1 - VLSI 2.0: R&D Post MooreSani Nassif, Yale N. Patt, Magdy S. Abadir. [doi]
- A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stageAli Fazli Yeknami, Atila Alvandpour. 1-6 [doi]
- A new compact analog VLSI model for Spike Timing Dependent PlasticityMostafa Rahimi Azghadi, Said F. Al-Sarawi, Nicolangelo Iannella, Derek Abbott. 7-12 [doi]
- Fully electronically programmable complex filter for multistandard applicationsHussain A. Alzaher, Noman Tasadduq. 13-18 [doi]
- Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combinersRicardo Povoa, Nuno C. Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes. 19-22 [doi]
- Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCsHussein Adel, Marie-Minerve Louërat, Marc Sabut. 23-26 [doi]
- A real-time 720p feature extraction core based on Semantic Kernels BinarizedMichael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin. 27-32 [doi]
- n±1 residue generatorsKostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi. 33-38 [doi]
- An area-efficient minimum-time FFT schedule using single-ported memoryStephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz. 39-44 [doi]
- An inverter-based neural amplifier for neural spike detectionSungho Kim, Urs Frey. 45-49 [doi]
- Effects of the positive feedback loop in self biased bandgap reference circuitsKemal Ozanoglu, Selçuk Talay. 50-51 [doi]
- Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineeringSharareh Zamanzadeh, Ali Jahanian. 52-53 [doi]
- Graph based fault model definition for bus testingElmira Karimi, Mohamad Hashem Haghbayan, Adele Maleki, Mahmoud Tabandeh. 54-55 [doi]
- On the accuracy of Monte Carlo yield estimatorsAlp Arslan Bayrakci. 56-57 [doi]
- High-speed Binary Signed-Digit RNS adder with posibit and negabit encodingSomayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev. 58-59 [doi]
- Implementation of Neuro-Fuzzy System based image edge detectionManel Elloumi, Mohamed Krid, Dorra Sellami Masmoudi. 60-61 [doi]
- Step response analysis of third order OpAmps With slew-rateMohsen Hassanpourghadi, Mohammad Sharifkhani. 62-63 [doi]
- Multi-band tunable low noise amplifiers operating at 850MHz and 1900MHz standardsFarshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Abd Manaf, Othman Sidek. 64-65 [doi]
- Analog layer extensions for analog/mixed-signal assertion languagesDogan Ulus, Alper Sen 0001, I. Faik Baskaya. 66-71 [doi]
- SyntHorus-2: Automatic prototyping from PSLKatell Morin-Allory, Fatemeh Negin Javaheri, Dominique Borrione. 72-77 [doi]
- A debugging method for gate level circuit designs by introducing programmabilityKosuke Oshima, Takeshi Matsumoto, Masahiro Fujita. 78-83 [doi]
- On the development of diagnostic test programs for VLIW processorsDavide Sabena, Matteo Sonza Reorda, Luca Sterpone. 84-89 [doi]
- New techniques for selecting test frequencies for linear analog circuitsMohand Bentobache, Ahcène Bounceur, Reinhardt Euler, Yann Kieffer, Salvador Mir. 90-95 [doi]
- Thermal-aware test scheduling for NOC-based 3D integrated circuitsDong Xiang, Gang Liu, Krishnendu Chakrabarty, Hideo Fujiwara. 96-101 [doi]
- Power-aware SoC test optimization through dynamic voltage and frequency scalingVijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal. 102-107 [doi]
- FOF: Functionally Observable Fault and its ATPG techniquesMasahiro Fujita, Takeshi Matsumoto, Satoshi Jo. 108-111 [doi]
- Minimization of EP-SOPs via Boolean relationsAnna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa. 112-117 [doi]
- A basic-block power annotation approach for fast and accurate embedded software power estimationChien-Min Lee, Chi-Kang Chen, Ren-Song Tsay. 118-123 [doi]
- A framework for Compiler Level statistical analysis over customized VLIW architectureAmir Hossein Ashouri, Vittorio Zaccaria, Sotirios Xydis, Gianluca Palermo, Cristina Silvano. 124-129 [doi]
- Data re-allocation enabled cache locking for embedded systemsKeni Qiu, Mengying Zhao, Chenchen Fu, Chun Jason Xue. 130-133 [doi]
- GR-PA: A cost pre-allocation model for global routingLeandro Nunes, Tiago Reimann, Ricardo Reis. 134-137 [doi]
- Gate sizing in the presence of gate switching activity and input vector controlNathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak. 138-143 [doi]
- An accurate power estimation model for low-power hierarchical-architecture SRAMsYuan Ren, Tobias G. Noll. 144-149 [doi]
- Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuitsHailong Jiao, Volkan Kursun. 150-155 [doi]
- Performance-driven SRAM macro design with parameterized cell considering layout-dependent effectsYu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake. 156-161 [doi]
- Gate-controlled doping in carbon-based FETsJoachim Knoch, Thomas Grap, Marcel Muller. 162-167 [doi]
- Fine grain multi-VT co-integration methodology in UTBB FD-SOI technologyBertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné. 168-173 [doi]
- Spin-electronics based logic fabricsWeisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert. 174-179 [doi]
- Reconfigurable photonic switching: Towards all-optical FPGAsSébastien Le Beux, Zhen Li, Christelle Monat, Xavier Letartre, Ian O'Connor. 180-185 [doi]
- Architecture and implementation of real-time 3D stereo vision on a Xilinx FPGASotiris Thomas, Kyprianos Papadimitriou, Apostolos Dollas. 186-191 [doi]
- Three-dimensional stacking FPGA architecture using face-to-face integrationTetsuro Hamada, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 192-197 [doi]
- Implementation of core coalition on FPGAsKaushik Triyambaka Mysur, Mihai Pricopi, Thomas Marconi, Tulika Mitra. 198-203 [doi]
- Low cost FPGA design and implementation of a stereo matching system for 3D-TV applicationsAydin Aysu, Murat Sayinta, Cevahir Cigla. 204-209 [doi]
- Dynamic cache pooling for improving energy efficiency in 3D stacked multicore processorsJie Meng, Tiansheng Zhang, Ayse Kivilcim Coskun. 210-215 [doi]
- Energy impact in the design space exploration of loop buffer schemes in embedded systemsAntonio Artés, José Luis Ayala, Robert Fasthuber, Praveen Raghavan, Francky Catthoor. 216-221 [doi]
- Adapting the columns of storage components for lower static energy dissipationMehmet Burak Aykenar, Muhammet Ozgur, Osman Seckin Simsek, Oguz Ergin. 222-227 [doi]
- Static energy minimization of 3D stacked L2 cache with selective cache compressionJongbum Park, Jongpil Jung, Kang Yi, Chong-Min Kyung. 228-233 [doi]
- New scan-based attack using only the test modeSk Subidh Ali, Ozgur Sinanoglu, Samah Mohamed Saeed, Ramesh Karri. 234-239 [doi]
- Examining Thread Vulnerability analysis using fault-injectionIsil Oz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir, Oguz Tosun. 240-245 [doi]
- A direct measurement scheme of amalgamated aging effects with novel on-chip sensorNicoleta Cucu Laurenciu, Yao Wang, Sorin Dan Cotofana. 246-251 [doi]
- IP-core protection for a non-volatile Self-reconfiguring SoC environmentWael Adi, S. Zeitouni, X. Huang, Marc Fyrbiak, Christan Kison, Marc Jeske, Z. Alnahhas. 252-255 [doi]
- Online periodic test mechanism for homogeneous many-core processorsArezoo Kamran, Zainalabedin Navabi. 256-259 [doi]
- Generating fast logic circuits for m-select n-port Round Robin ArbitrationH. Fatih Ugurdag, Fatih Temizkan, Sezer Gören. 260-265 [doi]
- Fine grain word length optimization for dynamic precision scaling in DSP systemsSeogoo Lee, Andreas Gerstlauer. 266-271 [doi]
- Compressed look-up-table based real-time rectification hardwareAbdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle, Alexandre Schmid, Yusuf Leblebici. 272-277 [doi]
- An energy efficient time-sharing pyramid pipeline for multi-resolution computer visionQiuling Zhu, Navjot Garg, Yun-Ta Tsai, Kari Pulli. 278-281 [doi]
- A high performance and low energy hardware for intra prediction with Template MatchingYusuf Adibelli, Ilker Hamzaoglu. 282-285 [doi]
- Processors as SoC building blocksYankin Tanurhan, Pieter van der Wolf. 286-287 [doi]
- Software-programmable digital pre-distortion on the Zynq SoCBaris Özgül, Jan Langer, Juanjo Noguera, Kees Visses. 288-289 [doi]
- Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the ZynqAntonio Filgueras, Eduard Gil, Carlos Alvarez, Daniel Jiménez-González, Xavier Martorell, Jan Langer, Juanjo Noguera. 290-291 [doi]
- Automatic mapping of OpenCV based systems on new heterogeneous SoCsFrancisco-Jose Sanchis-Cases, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi. 292-293 [doi]
- Accelerating software radio: Iris on the Zynq SoCJonathan van de Belt, Paul D. Sutton, Linda Doyle. 294-295 [doi]
- Staggered latch bus: A reliable offset switched architecture for long on-chip interconnectMelvin Eze, Ozcan Ozturk, Vijaykrishnan Narayanan. 296-301 [doi]
- Architectural exploration of a fine-grained 3D cache for high performance in a manycore contextEric Guthmuller, Ivan Miro Panades, Alain Greiner. 302-307 [doi]
- A power-efficient hierarchical network-on-chip topology for stacked 3D ICsDebora Matos, Cezar Reinbrecht, Tiago Motta, Altamiro Amadeu Susin. 308-313 [doi]
- PFT - A low overhead predictability enhancement technique for non-preemptive NoCsBharath Sudev, Leandro Soares Indrusiak. 314-317 [doi]
- FPGA vs DSP: A throughput and power efficiency comparison for Hierarchical Enumerative CodingYuhui Bai, Syed Zahid Ahmed, Imen Mhedhbi, Khalil Hachicha, Cedric Champion, Patrick Garda, Bertrand Granado. 318-321 [doi]
- PVT variation detection and compensation methods for high-speed systemsVazgen Melikyan, Abraham Balabanyan, Armen Durgaryan, Harutyun Stepanyan, Karen Sloyan, Hovik Musayelyan, Gayane Markosyan. 322-327 [doi]
- Towards the least complex time-multiplexed constant multiplicationLevent Aksoy, Paulo F. Flores, José C. Monteiro. 328-331 [doi]
- Analysis of Ring Oscillator structures to develop a design methodology for RO-PUF circuitsGiray Kömürcü, Ali Emre Pusane, Günhan Dündar. 332-335 [doi]
- Improved read voltage margins with alternative topologies for memristor-based crossbar memoriesIoannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis. 336-339 [doi]
- Decentralized self-balancing systemsSoumya Banerjee, Kai Da Zhao, Wenjing Rao, Milos Zefran. 340-343 [doi]
- A framework to accelerate sequential programs on homogeneous multicoresChristopher W. Fletcher, Rachael Harding, Omer Khan, Srinivas Devadas. 344-347 [doi]
- Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADCYajuan He, Bo Chen, Qiang Li. 348-351 [doi]
- Analog-to-digital converters power dissipation limits of CBSC-based pipelinedMajid Zamani, Clemens Eder, Andreas Demosthenous. 352-357 [doi]
- Variation-aware and adaptive-latency accesses for reliable low voltage cachesPo-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen. 358-363 [doi]
- 7.72 ppm/°C, ultralow power, high PSRR CMOS bandgap reference voltageAssia Hamouda, Ruediger Arnold, Otto Manck, Nour-Eddine Bouguechal. 364-367 [doi]
- Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit designAmr Tosson, Siddharth Garg, Mohab Anis. 368-373 [doi]
- Automatic addition of reset in asynchronous sequential control circuitsVikas S. Vij, Kenneth S. Stevens. 374-379 [doi]
- A 65-nm CMOS area optimized de-synchronization flow for sub-VT designsChristoph Muller, Steffen Malkowsky, Oskar Andersson, Babak Mohammadi, Jens Sparsø, Joachim Neves Rodrigues. 380-385 [doi]
- A center-aligned digital pulse-width modulator for envelope modulation of polar transmittersChien-Hung Kuo, Cin-De Jhang. 386-389 [doi]