J. Paul Roth - researchr alias

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Viewing Publication 1 - 13 from 13

1986

Minimization by the ::::D:::: AlgorithmJ. Paul Roth. TC, 35(5):476-478, 1986.

1984

VLSI Verification and CorrectionJ. Paul Roth. vlsi 1984: 174-176

Test Generation for FET Switching CircuitsJ. Paul Roth, Vojin G. Oklobdzija, John F. Beetem. itc 1984: 59-62

1978

Programmed Logic Array OptimizationJ. Paul Roth. TC, 27(2):174-176, 1978.

1977

Hardware VerificationJ. Paul Roth. TC, 26(12):1292-1294, 1977.

1972

Design of diagnosible automataJ. Paul Roth. acm 1972: 368 [doi]

1971

Algorithms for Detection of Faults in Logic CircuitsWillard G. Bouricius, Edward P. Hsieh, Gianfranco R. Putzolu, J. Paul Roth, Peter R. Schneider, Chung-Jen Tan. TC, 20(11):1258-1264, 1971. [doi]

A Heuristic Algorithm for the Testing of Asynchronous CircuitsGianfranco R. Putzolu, J. Paul Roth. TC, 20(6):639-647, 1971. [doi]

1970

R70-12 Diagnosis of Single-Gate Failures in Combinational CircuitsJ. Paul Roth. TC, 19(6):564-565, 1970. [doi]

1967

Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic CircuitsJ. Paul Roth, Willard G. Bouricius, Peter R. Schneider. TC, 16(5):567-580, 1967. [doi]

1962

Minimization Over Boolean GraphsJ. Paul Roth, Richard M. Karp. ibmrd, 6(2):227-238, 1962. [doi]

1960

Minimization over Boolean TreesJ. Paul Roth. ibmrd, 4(5):543-558, 1960. [doi]

1959

Algebraic Topological Methods for the Synthesis of Switching Systems - Part III: Minimization of Nonsingular Boolean TreesJ. Paul Roth, Eric G. Wagner. ibmrd, 3(4):326-344, 1959. [doi]

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