Interaction between Compilers and Computer Architectures - researchr conference series publications

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Viewing Publication 1 - 62 from 62

2012

16th Workshop on Interaction between Compilers and Computer Architectures, INTERACT 2012, New Orleans, LA, USA, February 25, 2012IEEE Computer Society, 2012. [doi]

Doubling the number of registers on ARM processorsHsu-Hung Chiang, Huang-Jia Cheng, Yuan-Shin Hwang. IEEEinteract 2012: 1-8 [doi]

Enhancing LRU replacement via phantom associativityMin Feng, Chen Tian, Rajiv Gupta. IEEEinteract 2012: 9-16 [doi]

Understand and categorize dynamically dead instructions for contemporary architecturesMarianne J. Jantz, Prasad A. Kulkarni. IEEEinteract 2012: 25-32 [doi]

Cooperative heterogeneous computing for parallel processing on CPU/GPU hybridsChangmin Lee, Won Woo Ro, Jean-Luc Gaudiot. IEEEinteract 2012: 33-40 [doi]

MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad MemoryQing'an Li, Yingchao Zhao, Jingtong Hu, Chun Jason Xue, Edwin Hsing-Mean Sha, Yanxiang He. IEEEinteract 2012: 17-24 [doi]

Lazy reference counting for the microgridRaphael Poss, Clemens Grelck, Stephan Herhut, Sven-Bodo Scholz. IEEEinteract 2012: 41-48 [doi]

2011

On-Line Trace Based Automatic Parallelization of Java Programs on Multicore PlatformsYu Sun 0006, Wei Zhang 0002. IEEEinteract 2011: 35-43 [doi]

15th Workshop on Interaction between Compilers and Computer Architectures, INTERACT 2011, San Antonio, Texas, USA, February 12, 2011IEEE Computer Society, 2011. [doi]

A Constraint Programming Approach for Instruction AssignmentMirza Beg, Peter van Beek. IEEEinteract 2011: 25-34 [doi]

A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional UnitAbhishek Deb, Josep M. Codina, Antonio González. IEEEinteract 2011: 1-8 [doi]

Improving Low Power Processor Efficiency with Static PipeliningIan Finlayson, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson. IEEEinteract 2011: 17-24 [doi]

Characterizing the Performance and Energy Efficiency of Lock-Free Data StructuresNicholas Hunt, Paramjit Singh Sandhu, Luis Ceze. IEEEinteract 2011: 63-70 [doi]

JIT Compilation Policy on Single-Core and Multi-core MachinesPrasad A. Kulkarni, Jay Fuller. IEEEinteract 2011: 54-62 [doi]

Aggressive Function Splitting for Partial InliningJunpyo Lee, Jae-Jin Kim, Soo-Mook Moon, Suhyun Kim. IEEEinteract 2011: 80-86 [doi]

The Good Block: Hardware/Software Design for Composable, Block-Atomic ProcessorsBertrand A. Maher, Katherine E. Coons, Kathryn S. McKinley, Doug Burger. IEEEinteract 2011: 9-16 [doi]

Implications of Program Phase Behavior on Timing AnalysisArchana Ravindar, Y. N. Srikant. IEEEinteract 2011: 71-79 [doi]

MATLAB Parallelization through ScalarizationChun-Yu Shei, Adarsh Yoga, Madhav Ramesh, Arun Chauhan. IEEEinteract 2011: 44-53 [doi]

2005

9th Annual Workshop on Interaction between Compilers and Computer Architectures, INTERACT-9 2005, San Francisco, California, USA, February 13, 2005IEEE Computer Society, 2005. [doi]

A tile size selection analysis for blocked array layoutsEvangelia Athanasaki, Nectarios Koziris, Panayotis Tsanakas. IEEEinteract 2005: 70-80 [doi]

Optimizing structures in object oriented programsKaiyu Chen, Sun Chan, Roy Dz-Ching Ju, Peng Tu. IEEEinteract 2005: 94-103 [doi]

Multigrain parallel processing on compiler cooperative chip multiprocessorKeiji Kimura, Yasutaka Wada, Hirofumi Nakano, Takeshi Kodaka, Jun Shirako, Kazuhisa Ishizaka, Hironori Kasahara. IEEEinteract 2005: 11-20 [doi]

Automatic low overhead program instrumentation with the LOPI frameworkSimon Kågström, Håkan Grahn, Lars Lundberg. IEEEinteract 2005: 82-93 [doi]

An empirical study of data speculation use on the Intel Itanium 2 processorMarkus Mock, Ricardo Villamarín-Salomón, José Baiocchi. IEEEinteract 2005: 22-33 [doi]

Compiler analysis for trace-level speculative multithreaded architecturesCarlos Molina, Antonio González, Jordi Tubella. IEEEinteract 2005: 2-10 [doi]

Cooperative caching with keep-me and evict-meJennifer B. Sartor, Subramaniam Venkiteswaran, Kathryn S. McKinley, Zhenlin Wang. IEEEinteract 2005: 46-57 [doi]

Analysis of path profiling information generated with performance monitoring hardwareAlex Shye, Matthew Iyer, Tipp Moseley, David Hodgdon, Dan Fay, Vijay Janapa Reddi, Daniel A. Connors. IEEEinteract 2005: 34-43 [doi]

Hybrid compiler and microarchitecture technique for cache traffic optimizationMohamed M. Zahran, Anasua Bhowmik. IEEEinteract 2005: 58-69 [doi]

2004

8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 15 February 2004, Madrid, SpainIEEE Computer Society, 2004.

Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache LocalityEvangelia Athanasaki, Nectarios Koziris. IEEEinteract 2004: 109-119 [doi]

Exploiting Procedure Level Locality to Reduce Instruction Cache MissesRavi V. Batchu, Daniel A. Jiménez. IEEEinteract 2004: 75-84 [doi]

Link-Time Optimization Techniques for Eliminating Conditional Branch RedundanciesManel Fernández, Roger Espasa. IEEEinteract 2004: 87-96 [doi]

Data Movement Optimization for Software-Controlled On-Chip MemoryMotonobu Fujita, Masaaki Kondo, Hiroshi Nakamura. IEEEinteract 2004: 120-127 [doi]

Exploitation of Instruction-Level Parallelism for Optimal Loop SchedulingJan Müller, Dirk Fimmel, Renate Merker. IEEEinteract 2004: 13-21 [doi]

Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded SystemsGilles Pokam, François Bodin. IEEEinteract 2004: 53-62 [doi]

Reducing Fetch Architecture Complexity Using Procedure InliningOliverio J. Santana, Alex Ramírez, Mateo Valero. IEEEinteract 2004: 97-106 [doi]

SimSnap: Fast-Forwarding via Native Execution and Application-Level CheckpointingPeter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz. IEEEinteract 2004: 65-74 [doi]

Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy ReductionOsman S. Unsal, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. IEEEinteract 2004: 43-52 [doi]

Dynamic Management of Nursery Space Organization in Generational CollectionJosé Manuel Velasco, Antonio Ortiz, Katzalin Olcoz, Francisco Tirado. IEEEinteract 2004: 33-40 [doi]

Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded SystemsJosé Manuel Velasco, David Atienza, Francky Catthoor, Francisco Tirado, Katzalin Olcoz, Jose Manuel Mendias. IEEEinteract 2004: 25-32 [doi]

Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary TranslatoYoufeng Wu, Mauricio Breternitz Jr., Tevi Devor. IEEEinteract 2004: 3-12 [doi]

2003

7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 8 February 2003, Anaheim, CA, USAIEEE Computer Society, 2003.

Combining Software and Hardware Monitoring for Improved Power and Performance TuningEric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss. IEEEinteract 2003: 57-64 [doi]

A Region-Based Compilation InfrastructureYang Liu, Zhaoqing Zhang, Ruliang Qiao, Roy Dz-Ching Ju. IEEEinteract 2003: 75-84 [doi]

An Adiabatic Framework for a Low Energy µ-Architecture & CompilerPramod Ramarao, Akhilesh Tyagi. IEEEinteract 2003: 65-74 [doi]

Compiler Support for Dynamic Speculative Pre-ExecutionWon Woo Ro, Jean-Luc Gaudiot. IEEEinteract 2003: 14-26 [doi]

High Performance Code Generation through Lazy Activation RecordsManoranjan Satpathy, Rabi N. Mahapatra, Siddharth Choudhuri, Sachin V. Chitnis. IEEEinteract 2003: 37-50 [doi]

The Effect of Compiler Optimizations on Pentium 4 Power ConsumptionJohn S. Seng, Dean M. Tullsen. IEEEinteract 2003: 51-56 [doi]

Impact of JIT/JVM Optimizations on Java Application PerformanceK. Shiv, R. Iyer, C. Newburn, J. Dahlstedt, M. Lagergren, O. Lindholm. IEEEinteract 2003: 5-13 [doi]

Procedure Cloning and Integration for Converting Parallelism from Coarse to Fine GrainWon So, Alexander G. Dean. IEEEinteract 2003: 27-36 [doi]

Compiler-Directed Resource Management for Active Code RegionsRavikrishnan Sree, Alex Settle, Ian Bratt, Daniel A. Connors. IEEEinteract 2003: 85-94 [doi]

2002

6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USAIEEE Computer Society, 2002.

Mastering Startup Costs in Assembler-Based Compiled Instruction-Set SimulationRonan Amicel, François Bodin. IEEEinteract 2002: 39-44 [doi]

A Study on Data Allocation of On-Chip Dual Memory BanksJeonghun Cho, Jinhwan Kim, Yunheung Paek. IEEEinteract 2002: 68 [doi]

Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread IntegrationAlexander G. Dean. IEEEinteract 2002: 3-14 [doi]

Code Cache Management Schemes for Dynamic OptimizersKim M. Hazelwood, Michael D. Smith. IEEEinteract 2002: 102-110 [doi]

On the Predictability of Program Behavior Using Different Input Data SetsWei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yuan Chen. IEEEinteract 2002: 45 [doi]

Dynamically Scheduling VLIW Instructions with Dependency InformationSunghyun Jee, Kannappan Palaniappan. IEEEinteract 2002: 15 [doi]

Code Compression by Register Operand DependencyKelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung. IEEEinteract 2002: 91-101 [doi]

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium ProcessorsR. David Weldon, Steven S. Chang, Hong Wang 0003, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen. IEEEinteract 2002: 57-67 [doi]

Accuracy of Profile Maintenance in Optimizing CompilersYoufeng Wu. IEEEinteract 2002: 27-38 [doi]

Code Size Efficiency in Global Scheduling for ILP ProcessorsHuiyang Zhou, Thomas M. Conte. IEEEinteract 2002: 79-90 [doi]

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