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Viewing Publication 1 - 100 from 582

2007

Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, GermanyIEEE, 2007.

Exploiting Parallelism in Double Path Adders Structure for Increased Throughput of Floating Point AdditionAlexandru Amaricai, Mircea Vladutiu, Lucian Prodan, Mihai Udrescu, Oana Boncalo. dsdm 2007: 132-137 [doi]

Design and Implementation of a 50MHZ DXT CoProcessorMohammad Amin Amiri, Reza Ebrahimi Atani, Sattar Mirzakuchaki, Mojdeh Mahdavi. dsdm 2007: 43-50 [doi]

A Serial Logarithmic Number System ALUMark G. Arnold, Panagiotis D. Vouzis. dsdm 2007: 151-156 [doi]

P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applicationsIsmail Assayad, Sergio Yovine. dsdm 2007: 181-188 [doi]

FPGA/DSP-based Configurable Multi-Channel CounterD. Audino, F. Baronti, A. Lazzeri, Roberto Roncella, Roberto Saletti. dsdm 2007: 376-382 [doi]

Adaptive Distance Estimation and Localization in WSN using RSSI MeasuresAbdalkarim Awad, Thorsten Frunzke, Falko Dressler. dsdm 2007: 471-478 [doi]

OOCE: Object-Oriented Communication Engine for SoC DesignJesús Barba, Fernando Rincón, Francisco Moya, Felix Jesús Villanueva, David Villa, Julio Dondo, Juan Carlos López. dsdm 2007: 296-302 [doi]

Evaluating Energy Consumption in Wireless Sensor Networks ApplicationsAgustin Barberis, Leonardo Barboni, Maurizio Valle. dsdm 2007: 455-462 [doi]

The Criteria of Functional Delay Test Quality AssessmentEduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas. dsdm 2007: 207-214 [doi]

The importance of At-Speed Scan Testing: an industrial experienceF. Baronti, Roberto Roncella, Roberto Saletti, P. D Abramo, L. Di Piro, H. Fabian, M. Giardi. dsdm 2007: 672-675 [doi]

A Hardware-Software Platform for Design and Verification of In-Motorcycle Electronic SystemsF. Baronti, F. Lenzi, Roberto Roncella, Roberto Saletti. dsdm 2007: 440-443 [doi]

A Run-Time Scheduling Framework for a Reconfigurable Hardware EmulatorRene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt. dsdm 2007: 147-150 [doi]

Ulta-Low-Power Wireless Sensor Node Design on 100 uW Scavenging Energy for Applications In Biomedical MonitoringMladen Berekovic. dsdm 2007: 16-18 [doi]

Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance AssessmentOana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai. dsdm 2007: 634-640 [doi]

NoC Topologies Exploration based on Mapping and Simulation ModelsLuciano Bononi, Nicola Concer, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli. dsdm 2007: 543-546 [doi]

MPSoC memory optimization for digital camera applicationsYoucef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin. dsdm 2007: 424-427 [doi]

A New Framework for Design and Simulation of Complex Hardware/Software SystemsCarlo Brandolese, D. Crespi, Laura Frigerio, Fabio Salice. dsdm 2007: 236-243 [doi]

Semiconductor and EDA Challenges: Still Lots To Solve!Chi-Foon Chan. dsdm 2007: 4 [doi]

Component-Based Hardware/Software Co-SimulationPing Hang Cheung, Kecheng Hao, Fei Xie. dsdm 2007: 265-270 [doi]

Architecture of a Small Low-Cost SatelliteDante Del Corso, Claudio Passerone, Leonardo Maria Reyneri, Claudio Sansoè, Marco Borri, Stefano Speretta, Maurizio Tranchero. dsdm 2007: 428-431 [doi]

Design and Implementation of a 90nm Low bit-rate Image Compression CorePasquale Corsonello, Stefania Perri, G. Staino, Marco Lanuzza, Giuseppe Cocorullo. dsdm 2007: 383-389 [doi]

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM ProcessMinh Quang Do, Per Larsson-Edefors, Mindaugas Drazdziulis. dsdm 2007: 249-256 [doi]

Architecture Exploration of 3D Video Recorder Using Virtual Platform ModelsMatti Eteläperä, Janne Vatjus Anttila, Juha Pekka Soinimen. dsdm 2007: 404-411 [doi]

On the Construction of Small Fully Testable Circuits with Low DepthGörschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler. dsdm 2007: 563-569 [doi]

Security Aspects in Networks-on-Chips: Overview and Proposals for Secure ImplementationsLeandro Fiorin, Cristina Silvano, Mariagiovanna Sami. dsdm 2007: 539-542 [doi]

Pseudo-Random Pattern Generator Design for Column-Matching BISTPetr Fiser. dsdm 2007: 657-663 [doi]

A Sliced Coprocessor for Native Clifford Algebra OperationsS. Franchini, Antonio Gentile, M. Grimaudo, C. A. Hung, Sandro Impastato, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile. dsdm 2007: 436-439 [doi]

Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC CodesGiuseppe Gentile, Massimo Rovini, Luca Fanucci. dsdm 2007: 369-375 [doi]

Latency Minimization for Synchronous Data Flow GraphsAmir Hossein Ghamarian, Sander Stuijk, Twan Basten, Marc Geilen, Bart D. Theelen. dsdm 2007: 189-196 [doi]

A Robust GF(p) Parallel Arithmetic Unit for Public Key CryptographySantosh Ghosh, Monjur Alam, Indranil Sengupta, Dipanwita Roy Chowdhury. dsdm 2007: 109-115 [doi]

On Complexity of Internal and External Equivalence CheckingEugene Goldberg, Kanupriya Gulati. dsdm 2007: 197-206 [doi]

Toggle Equivalence Preserving (TEP) Logic OptimizationEugene Goldberg, Kanupriya Gulati, Sunil P. Khatri. dsdm 2007: 271-279 [doi]

FPGA-based Road Traffic VideodetectorMarek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo. dsdm 2007: 412-419 [doi]

Performance Evaluation of Instruction Set Extensions for Long Integer Modular Arithmetic on a SPARC V8 ProcessorJohann Großschädl, Stefan Tillich, Alexander Szekely. dsdm 2007: 680-689 [doi]

Merge Logic for Clustered Multithreaded VLIW ProcessorsManoj Gupta, Fermín Sánchez, Josep Llosa. dsdm 2007: 353-360 [doi]

Experiences with a FPGA-based Reed/Solomon Encoding CoprocessorVolker Hampel, Peter Sobe, Erik Maehle. dsdm 2007: 77-84 [doi]

A resource optimized Processor Core for FPGA based SoCsGerald Hempel, Christian Hochberger. dsdm 2007: 51-58 [doi]

Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault EnvironmentChristian J. Hescott, Drew C. Ness, David J. Lilja. dsdm 2007: 641-648 [doi]

Evaluating the Model Accuracy in Automated Design Space ExplorationKalle Holma, Mikko Setälä, Erno Salminen, Timo D. Hämäläinen. dsdm 2007: 173-180 [doi]

Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM SystemsNicola E. L Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni. dsdm 2007: 361-368 [doi]

A New Class of Cellular AutomataHosna Jabbari, Jon C. Muzio, Lin Sun. dsdm 2007: 331-338 [doi]

A FPGA Optimised Digital Real-Time Mutichannel Correlator ArchitectureChristian Jakob, A. Th. Schwarzbacher, Bernhard Hoppe, R. Peters. dsdm 2007: 35-42 [doi]

Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting DevicesAlex Janek, Christoph Trummer, Christian Steger, Reinhold Weiss, Josef Preishuber-Pfluegl, Markus Pistauer. dsdm 2007: 463-462 [doi]

Hybrid BIST Optimization Using Reseeding and Test Set CompactionGert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar. dsdm 2007: 596-603 [doi]

Functional Test-Case Generation by a Control Transaction Graph for TLM VerificationMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Siamak Mohammadi. dsdm 2007: 157-164 [doi]

On-Chip Verification of NoCs Using Assertion ProcessorsMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi. dsdm 2007: 535-538 [doi]

Proving Completeness of Properties in Formal Verification of Counting Heads for RailwaysSebastian Kinder, Rolf Drechsler. dsdm 2007: 396-403 [doi]

Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAsAndrzej Krasniewski. dsdm 2007: 579-586 [doi]

Power Estimation of Time Variant SoCs with TAPESAndreas Lankes, Thomas Wild, Johannes Zeppenfeld. dsdm 2007: 261-264 [doi]

A Proposal of New Join Operators for Sensor Network DatabasesSeungjae Lee, Changhwa Kim, Sangkyung Kim. dsdm 2007: 479-484 [doi]

FATTY: A Reliable FAT File SystemAlei Liang, Kejia Liu, Xiaoyong Li, Haibing Guan. dsdm 2007: 390-395 [doi]

An Embedded Implementation of the Microsoft Common Language InfrastructureJoseph C. Libby, Kenneth B. Kent. dsdm 2007: 165-172 [doi]

A DRAM Precharge Policy Based on Address AnalysisChiyuan Ma, Shuming Chen. dsdm 2007: 244-248 [doi]

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layerD. Mangano, G. Falconeri, C. Pistritto, A. Scandurra. dsdm 2007: 519-526 [doi]

A Low Power Information Redundant Concurrent Error Detecting Asynchronous ProcessorM. Marshall, G. Russell. dsdm 2007: 649-656 [doi]

Graph Matching Constraints for Synthesis with Complex ComponentsAna Fuentes Martinez, Krzysztof Kuchcinski. dsdm 2007: 288-295 [doi]

On the impact of serialization on the cache performances in Network-on-Chip based MPSoCsPaolo Meloni, Giovanni Busonera, Salvatore Carta, Luigi Raffo. dsdm 2007: 556-562 [doi]

Increasing NoC Performance and Utilisation using a Dual Packet Exit StrategyMikael Millberg, Axel Jantsch. dsdm 2007: 511-518 [doi]

Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate ArraysScott Miller, Mihai Sima, Michael McGuire. dsdm 2007: 138-146 [doi]

An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic ModelsMohammad Mirza-Aghatabar, Somayyeh Koohi, Shaahin Hessabi, Massoud Pedram. dsdm 2007: 19-26 [doi]

Fault Injection Techniques and their Accelerated Simulation in SystemCSilvio Misera, Heinrich Theodor Vierhaus, André Sieber. dsdm 2007: 587-595 [doi]

An On-Line BIST Technique for Stuck-Open Fault Detection in CMOS CircuitsElham K. Moghaddam, Shaahin Hessabi. dsdm 2007: 619-625 [doi]

Decoupling of Computation and Communication with a Communication AssistArno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen. dsdm 2007: 63-68 [doi]

Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA ImplementationShinobu Nagayama, Tsutomu Sasao, Jon T. Butler. dsdm 2007: 280-287 [doi]

A Hardware/Software Co-design vs. Hardware Implementation of the Modular Exponentiation Using the Sliding-Window Method with Constant-Length PartitioningNadia Nedjah, Luiza de Macedo Mourelle. dsdm 2007: 116-123 [doi]

General Digit-Serial Normal Basis Multiplier with Distributed OverlapMartin Novotný, Jan Schmidt. dsdm 2007: 94-101 [doi]

An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion EstimationSerkan Oktem, Ilker Hamzaoglu. dsdm 2007: 444-447 [doi]

Application-Specific Topology Design Customization for STNoCGianluca Palermo, Cristina Silvano, Giovanni Mariani, Riccardo Locatelli, Marcello Coppola. dsdm 2007: 547-550 [doi]

Silicon Compaction/Defragmentation for Partial Runtime ReconfigurationKolin Paul, Joel Porquet, Josep Llosa. dsdm 2007: 317-324 [doi]

Execution-time Prediction for Dynamic Streaming Applications with Task-level ParallelismPeter Poplavko, Twan Basten, Jef L. van Meerbergen. dsdm 2007: 228-235 [doi]

Design Without BordersJan M. Rabaey. dsdm 2007: 3 [doi]

Short Distance Wireless, Dense Networks, and Their OpportunitiesJan M. Rabaey, Yuen-Hui Chee, David Chen, Luca De Nardis, Simone Gambini, Davide Guermandi, Michael Mark, Nathan Pletcher. dsdm 2007: 7 [doi]

Hierarchical Identification of Untestable Faults in Sequential CircuitsJaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus. dsdm 2007: 668-671 [doi]

Novel Agent-Based Management for Fault-Tolerance in Network-on-ChipPekka Rantala, Jouni Isoaho, Hannu Tenhunen. dsdm 2007: 551-555 [doi]

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI InterconnectsJ. V. R. Ravindra, M. B. Srinivas. dsdm 2007: 325-330 [doi]

Test Controller Synthesis Constrained by Circuit Testability AnalysisRichard Ruzicka, Josef Strnadel. dsdm 2007: 626-633 [doi]

Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic SynthesisMehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi. dsdm 2007: 339-346 [doi]

An Efficient Intra Prediction Hardware Architecture for H.264 Video DecodingEsra Sahin, Ilker Hamzaoglu. dsdm 2007: 448-454 [doi]

Fault Handling in FPGAs and Microcontrollers in Safety-Critical Embedded Applications: A Comparative SurveyFalk Salewski, Adam Taylor. dsdm 2007: 124-131 [doi]

On network-on-chip comparisonErno Salminen, Ari Kulmala, Timo D. Hämäläinen. dsdm 2007: 503-510 [doi]

An Implementation of an Address Generator Using Hash MemoriesTsutomu Sasao, Munehiro Matsuura. dsdm 2007: 69-76 [doi]

Analysis of Variable Reordering on the QMDD Representation of Quantum CircuitsSharon Van Schaick, Kenneth B. Kent. dsdm 2007: 347-352 [doi]

Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip ArchitecturesTimo Schönwald, Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel. dsdm 2007: 527-534 [doi]

An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error DetectorEmanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello. dsdm 2007: 102-108 [doi]

Functional Verification of RTL Designs driven by Mutation Testing metricsYoussef Serrestou, Vincent Beroulle, Chantal Robach. dsdm 2007: 222-227 [doi]

Testability Analysis Based on the Identification of Testable Blocks with Predefined PropertiesJaroslav Skarvada, Tomas Herrman, Zdenek Kotásek. dsdm 2007: 611-618 [doi]

Reducing the Overhead of Real-Time Operating System through Reconfigurable HardwareMoonvin Song, Sang Hoon Hong, Yunmo Chung. dsdm 2007: 311-316 [doi]

A Wireless Sensor Node Architecture Using Remote Power Charging, for Interaction ApplicationsMatthew D Souza, Konstanty Bialkowski, Adam Postula, Montserrat Ros. dsdm 2007: 485-494 [doi]

Safety and Security-driven Design of Networked Embedded SystemsMiroslav Svéda, Roman Trchalik. dsdm 2007: 420-423 [doi]

Online Protocol Testing for FPGA Based Fault Tolerant SystemsJiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka. dsdm 2007: 676-679 [doi]

Fault Diagnosis in Integrated Circuits with BISTRaimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen. dsdm 2007: 604-610 [doi]

Actas del Taller sobre Desarrollo de Software Dirigido por Modelos. MDA y Aplicaciones. Sitges, Spain, October 3, 2006Antonio Vallecillo, Vicente Pelechano, Antonio Estévez, editors, Volume 227 of CEUR Workshop Proceedings, CEUR-WS.org, 2007.

Streaming consistency: a model for efficient MPSoC designJan Willem van den Brand, Marco Bekooij. dsdm 2007: 27-34 [doi]

RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-ChipGuillermo Payá Vayá, Javier Martín-Langerwerf, Peter Pirsch. dsdm 2007: 215-221 [doi]

An Efficient BIST Scheme for Non-Restoring Array DividersHaridimos T. Vergos. dsdm 2007: 664-667 [doi]

Timing- / Power-Optimization for Digital Logic Based on Standard CellsHeinrich Theodor Vierhaus, Helmut Rossmann, Silvio Misera. dsdm 2007: 303-306 [doi]

Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS SubtractionPanagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold. dsdm 2007: 85-93 [doi]

Controller Design and Verification for A Pipeline Image Processor based on An Extended Petri netKatsumi Wasaki, Toshiaki Harai, Tamotsu Hayashi, Ken-ichi Arai. dsdm 2007: 257-260 [doi]

Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java MicroarchitectureMartin Zabel, Thomas B. Preuber, Peter Reichel, Rainer G. Spallek. dsdm 2007: 59-62 [doi]

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