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2002

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, JapanIEEE Computer Society, 2002.

Datapath Merging and Interconnection Sharing for Reconfigurable ArchitecturesGuido Araujo, Sharad Malik, Zhining Huang, Nahri Moreano. isss 2002: 38-43 [doi]

Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable ProcessorsNader Bagherzadeh, Pai H. Chou, Jinfeng Liu. isss 2002: 14-19 [doi]

Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip MemoryM. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke. isss 2002: 213-218 [doi]

A New Performance Evaluation Approach for System Level Design Space ExplorationM. Balakrishnan, Anshul Kumar, C. P. Joshi. isss 2002: 180-185 [doi]

A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional UnitsM. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha. isss 2002: 2-7 [doi]

Controller Estimation for FPGA Target Architectures during High-Level SynthesisOliver Bringmann, Wolfgang Rosenstiel, Carsten Menn. isss 2002: 56-61 [doi]

System-Level Modeling of a Network Switch SoCAndrew S. Cassidy, Christopher P. Andrews, Donald E. Thomas, JoAnn M. Paul. isss 2002: 62-67 [doi]

System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and MemoryAbhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy. isss 2002: 225-230 [doi]

Multiprocessor Mapping of Process Networks: A JPEG Decoding Case StudyErwin A. de Kock. isss 2002: 68-73 [doi]

Efficient Power Reduction Techniques for Time Multiplexed Address BusesNikil D. Dutt, Daniel S. Hirschberg, Mahesh Mamidipaka. isss 2002: 207-212 [doi]

The Formal Execution Semantics of SpecCRainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003. isss 2002: 150-155 [doi]

Formal Verification in a Component-Based Reuse MethodologyPetru Eles, Zebo Peng, Daniel Karlsson. isss 2002: 156-161 [doi]

Modeling Assembly Instruction Timing in Superscalar ArchitecturesWilliam Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame. isss 2002: 132-137 [doi]

Optimal Message-Passing for Data Coherency in Distributed ArchitectureDaniel Gajski, Junyu Peng. isss 2002: 20-25 [doi]

System-Level Abstraction SemanticsDaniel Gajski, Andreas Gerstlauer. isss 2002: 231-236 [doi]

Security-Driven Exploration of Cryptography in DSP CoresCatherine H. Gebotys. isss 2002: 80-85 [doi]

Efficient Simulation of Synthesis-Oriented System Level DesignsRajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu. isss 2002: 168-173 [doi]

Virtual Synchronization for Fast Distributed Cosimulation of Dataflow Task GraphsSoonhoi Ha, Sungchan Kim, Chan-Eun Rhee, Hyunguk Jung, Youngmin Yi, Dohyung Kim. isss 2002: 174-179 [doi]

An Adaptive Low-Power Transmission Scheme for On-Chip NetworksPaolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm. isss 2002: 92-100 [doi]

Round-Robin Arbiter Design and GenerationVincent John Mooney III, George F. Riley, Eung S. Shin. isss 2002: 243-248 [doi]

Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC DesignAhmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli. isss 2002: 26-31 [doi]

Validation in a Component-Based Design Flow for Multicore SoCsAhmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu. isss 2002: 162-167 [doi]

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia SystemsRudy Lauwereins, Chun Wong, Paul Marchal, Johan Vounckx, Patrick David, Stefaan Himpe, Francky Catthoor, Peng Yang. isss 2002: 112-119 [doi]

A Symbolic Approach for the Combined Solution of Scheduling and AllocationLuciano Lavagno, Mihai T. Lazarescu, Stefano Quer, Sergio Nocco, Claudio Passerone, Gianpiero Cabodi. isss 2002: 237-242 [doi]

Code Compression for VLIW Processors Using Variable-to-Fixed CodingHaris Lekatsas, Wayne Wolf, Yuan Xie. isss 2002: 138-143 [doi]

Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable CoprocessorsJuan Carlos López, Fernando Rincón, Francisco Moya, José Manuel Moya. isss 2002: 255-260 [doi]

Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional VerificationSatoshi Matsushita. isss 2002: 103-108 [doi]

An Object-Oriented Design Process for System-on-Chip Using UMLTsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya Kuwamura, Qiang Zhu. isss 2002: 249-254 [doi]

A Design Space Exploration Framework for Reduced Bit-Width Instruction Set Architecture (rISA) Design Alexandru Nicolau, Nikil D. Dutt, Aviral Shrivastava, Partha Biswas, Ashok Halambi. isss 2002: 120-125 [doi]

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level SynthesisAlexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Nick Savoiu, Mehrdad Reshadi, Sumit Gupta. isss 2002: 261-266 [doi]

System-Level Design of IEEE1394 Bus Segment BridgeTakao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto. isss 2002: 74-79 [doi]

Low-Power Data Memory Communication for Application-Specific Embedded ProcessorsAlex Orailoglu, Peter Petrov. isss 2002: 219-224 [doi]

Securing Wireless Data: System Architecture ChallengesAnand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi. isss 2002: 195-200 [doi]

Energy/Power Estimation of Regular Processor ArraysSanjay V. Rajopadhye, Steven Derrien. isss 2002: 50-55 [doi]

Timing Analysis of Embedded Software for Speculative ProcessorsAbhik Roychoudhury, Xianfeng Li, Tulika Mitra. isss 2002: 126-131 [doi]

A Visual Approach to Validating System Level DesignsJürgen Ruf, Thomas Kropf, Jochen Klose. isss 2002: 186-191 [doi]

CMP on SoC: Architect s ViewShuichi Sakai. isss 2002: 101-102 [doi]

A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW ProcessorCarles Rodoreda Sala, Natalino G. Busá. isss 2002: 44-49 [doi]

A Case Study of Hardware and Software Synthesis in ForSyDeIngo Sander, Axel Jantsch, Zhonghai Lu. isss 2002: 86-91 [doi]

OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-Chip MultiprocessorsMitsuhisa Sato. isss 2002: 109-111 [doi]

Tuning of Loop Cache Architectures to Programs in Embedded System DesignFrank Vahid, Susan Cotterell. isss 2002: 8-13 [doi]

Optimal Code Size Reduction for Software-Pipelined and Unfolded LoopsBin Xiao, Zili Shao, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Qingfeng Zhuge. isss 2002: 144-149 [doi]

Special Session: Security on SoCHiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys. isss 2002: 192-194 [doi]

An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded SystemsHiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin. isss 2002: 32-37 [doi]

Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded SystemsHiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao. isss 2002: 201-206 [doi]

2001

ISSS2001.

RTL semantics and methodologyBrian Bailey, Daniel Gajski. isss 2001: 69-74

Phase coupled operation assignment for VLIW processors with distributed register filesMarco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen. isss 2001: 118-123

Dynamic modeling of inter-instruction effects for execution time estimationGiovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni. isss 2001: 136-141

Powering networks on chipsLuca Benini, Giovanni De Micheli. isss 2001: 33-38

Performance analysis with confidence intervals for embedded software processesPer Bjuréus, Axel Jantsch. isss 2001: 45-50

On-line fault detection in a hardware/software co-design environmentCristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto. isss 2001: 51-56

Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine descriptionGunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr. isss 2001: 57-62

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniquesNoureddine Chabini, Yvon Savaria. isss 2001: 209-214

An energy efficient rate selection algorithm for voltage quantized dynamic voltage scalingLama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt. isss 2001: 124-129

Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faultsChien-In Henry Chen. isss 2001: 203-208

Retargetable static timing analysis for embedded softwareKaiyu Chen, Sharad Malik, David I. August. isss 2001: 39-44

Efficient instruction-level optimization methodology for low-power embedded systemsKyu-won Choi, Abhijit Chatterjee. isss 2001: 147-152

Source code transformation based on software cost analysisEui-Young Chung, Luca Benini, Giovanni De Micheli. isss 2001: 153-158

Control and communication performance analysis of embedded DSP systems in the MASIC methodologyAbhijit K. Deb, Johnny Öberg, Axel Jantsch. isss 2001: 274-273

Combined instruction and loop parallelism in array synthesis for FPGAsSteven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. isss 2001: 165-170

Interoperability as a design issue in C++ based modeling environmentsFrederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla. isss 2001: 87-92

Soft-cores generation by instruction set analysisAlessandro Fin, Franco Fummi, Giovanni Perbellini. isss 2001: 227-232

Loop fusion for memory space optimizationAntoine Fraboulet, Karen Kodary, Anne Mignotte. isss 2001: 95-100

The standard SpecC languageMasahiro Fujita, Hiroshi Nakamura. isss 2001: 81-86

A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systemsOm Prakash Gangwal, André Nieuwland, Paul E. R. Lippens. isss 2001: 1-6

Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC designGuang R. Gao. isss 2001: 93

APEXPeter Grun, Nikil D. Dutt, Alexandru Nicolau. isss 2001: 25-32

Conditional speculation and its effects on performance and area for high-level snthesisSumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. isss 2001: 171-176

Proceedings of the 14th International Symposium on Systems Synthesis, ISSS 2001, Montrél, Québec, Canada, September 30 - October 3, 2001Román Hermida, El Mostapha Aboulhamid, editors, ACM / IEEE Computer Society, 2001. [doi]

Programming models for network processors (Panel)Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld. isss 2001: 202

Exploiting scratch-pad memory using Presburger formulasMahmut T. Kandemir, Ismail Kadayif, Ugur Sezer. isss 2001: 7-12

Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOSAhmed Khoumsi. isss 2001: 268-273

Object oriented hardware synthesis and verificationTommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai. isss 2001: 189-194

Design and simulation of a pipelined decompression architecture for embedded systemsHaris Lekatsas, Jörg Henkel, Wayne Wolf. isss 2001: 63-68

High-level automatic pipelining for sequential circuitsMaria-Cristina V. Marinescu, Martin C. Rinard. isss 2001: 215-220

An optimal memory allocation for application-specific multiprocessor system-on-chipSamy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya. isss 2001: 19-24

Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applicationsMiguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest. isss 2001: 107-112

Functional abstraction driven design space exploration of heterogeneous programmable architecturesPrabhat Mishra, Nikil D. Dutt, Alexandru Nicolau. isss 2001: 256-261

Current consumption dynamics at instruction and program level for a ::::VLIW:::: DSP processorRadu Muresan, Catherine H. Gebotys. isss 2001: 130-135

System design of a telecommunication routerRichard Norman. isss 2001: 196

SystemCPreeti Ranjan Panda. isss 2001: 75-80

Cache-efficient memory layout of aggregate data structuresPreeti Ranjan Panda, Luc Séméria, Giovanni De Micheli. isss 2001: 101-106

Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing enginesJoonseok Park, Pedro C. Diniz. isss 2001: 221-226

Modeling and simulation of steady state and transient behaviors for emergent SoCsJoAnn M. Paul, Arne J. Suppé, Donald E. Thomas. isss 2001: 262-267

Embedded systems technologies for application-specific architecture platformsPierre G. Paulin. isss 2001: 195

Data cache energy minimizations through programmable tag size matching to the applicationsPeter Petrov, Alex Orailoglu. isss 2001: 113-117

New design paradigmsWolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda. isss 2001: 94

A data scheduler for multi-context reconfigurable architecturesMarcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh. isss 2001: 177-182

Considering power variations of DVS processing elements for energy minimisation in distributed systemsMarcus T. Schmitz, Bashir M. Al-Hashimi. isss 2001: 250-255

System level optimization and design space exploration for low powerAnsgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz. isss 2001: 142-146

System-level interconnect architecture exploration for custom memory organizationsTycho van Meeuwen, Arnout Vandecappelle, Allert van Zelst, Francky Catthoor, Diederik Verkest. isss 2001: 13-18

Network processing in content inspection applicationsFeliks J. Welfeld. isss 2001: 197-201

Static resource models of instruction setsQin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess. isss 2001: 159-164

Accelerating boolean satisfiability through application specific processingYing Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan. isss 2001: 244-249

Application of Software design patterns to DSP library designPontus Åström, Stefan Johansson, Peter Nilsson. isss 2001: 239-243

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