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2020

Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake ProtocolAmeer M. S. Abdelhadi. norchip 2020: 1-7 [doi]

Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder InterferometersShashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder. norchip 2020: 1-7 [doi]

Design of a Current Mode Multiplexed Circuit for Integrate & Fire Neuromorphic SystemsVincenzo Bonaiuto, Fausto Sargeni. norchip 2020: 1-6 [doi]

Low Power Class-AB Line Driver with Adaptive Digital Impedance Control for Fast EthernetSimon Buhr, Martin Kreißig, Christian D. Matthus, Florian Protze, Frank Ellinger. norchip 2020: 1-7 [doi]

Software-Defined Radio Assessment for Microwave Imaging Breast Cancer DetectionDionisio Carvalho, Alexandre J. Aragão, André Ferrari, Bruno Sanches, Wilhelmus A. M. Van Noije. norchip 2020: 1-6 [doi]

A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOSOscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek. norchip 2020: 1-4 [doi]

A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCsJessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker 0001. norchip 2020: 1-7 [doi]

On the Design of a CMOS-integrated Load Modulated Balanced AmplifierTed Johansson, Srivatsa Samji. norchip 2020: 1-4 [doi]

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft ErrorsServer Kasap, Eduardo Weber Wächter, Xiaojun Zhai, Shoaib Ehsan, Klaus D. McDonald-Maier. norchip 2020: 1-7 [doi]

Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCsMax Koenen, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf. norchip 2020: 1-7 [doi]

A 500 mV, 4.5 mW, 16 GHz VCO with 33.3% FTR, designed for 5G applicationsPiyush Kumar, Dario Stajic, Enno Böhme, Erkan Nevzat Isa, Linus Maurer. norchip 2020: 1-4 [doi]

A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural NetworkLizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng 0001. norchip 2020: 1-6 [doi]

A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking RangeMadhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder. norchip 2020: 1-5 [doi]

Model-Based Design Space Exploration for Approximate Image Processing on FPGAManu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele. norchip 2020: 1-7 [doi]

Digital Architecture for MUAPs Propagation Speed Estimator triggered by Foot Plant SwitchGiovanni Mezzina, Daniela De Venuto. norchip 2020: 1-7 [doi]

Digital Timing Error Calibration of Time-Interleaved ADC with Low Sample RateMarko Neitola. norchip 2020: 1-7 [doi]

IEEE Nordic Circuits and Systems Conference, NorCAS 2020, Oslo, Norway, October 27-28, 2020Jari Nurmi, Dag T. Wisland, Snorre Aunet, Kristian Kjelgaard, editors, IEEE, 2020. [doi]

A Parallel and Pipelined Implementation of a Pascal-Simplex Based Two Asset Option Pricer on FPGA using OpenCLAidan O'Mahony, Gil Zeidan, Bernard Hanzon, Emanuel M. Popovici. norchip 2020: 1-6 [doi]

A Low Power Front-end for Biomedical Fluorescence Sensing ApplicationsSeyed Ruhallah Qasemi, Maryam Rafati, Atila Alvandpour. norchip 2020: 1-6 [doi]

Schmitt Trigger Based Single-Ended Voltage Amplifier with Positive Feedback Control for Ultra-Low-Voltage SuppliesLuis Henrique Rodovalho. norchip 2020: 1-6 [doi]

Origins of Intermodulation Distortion in A Pseudo-differential CMOS Beamforming ReceiverNegar Shabanzadeh, Mahmoud Shehab, Rehman Akbar, Aarno Pärssinen, Timo Rahkonen. norchip 2020: 1-6 [doi]

A Power Efficient, High Gain and High Input Impedance Capacitively-coupled Neural AmplifierErwin H. T. Shad, Tania Moeinfard, Marta Molinas, Trond Ytterdal. norchip 2020: 1-5 [doi]

A Voltage Controlled Oscillator with Inductive Divider Design and Analysis at Frequencies Above 100 GHzYasir Shafiullah, Rehman Akbar, Mikko Hietanen, Aarno Pärssinen. norchip 2020: 1-5 [doi]

Matrix Decomposition for Massive MIMO DetectionShahriar Shahabuddin, Muhammad Hasibul Islam, Mohammad Shahanewaz Shahabuddin, Mahmoud A. M. Albreem, Markku J. Juntti. norchip 2020: 1-6 [doi]

HyVE: A Hybrid Voting-based Eviction Policy for CachesAkshay Srivatsa, Sebastian Nagel 0004, Nael Fasfous, Nguyen Anh Vu Doan, Thomas Wild, Andreas Herkersdorf. norchip 2020: 1-7 [doi]

A 10b 1GS/s Inverter-Based Pipeline ADC in 65nm CMOSTimmy Sundström, Javad Bagheri Asli, Christer Svensson, Atila Alvandpour. norchip 2020: 1-4 [doi]

A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCsSiyu Tan, Mattias Palm, Daniele Mastantuono, Roland Strandberg, Lars Sundström, Sven Mattisson, Pietro Andreani. norchip 2020: 1-6 [doi]

Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAsCornelia Wulf, Michael Willig, Diana Göhringer. norchip 2020: 1-7 [doi]

Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold AddersSomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. norchip 2020: 1-6 [doi]

Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI TechnologySomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. norchip 2020: 1-6 [doi]

2019

Two-Step Pipeline SAR ADC with passive Charge Sharing between CascadesDmitry Osipov 0001, Aleksandr Gusev, Steffen Paul, Vitaly Shumikhin. norchip 2019: 8138-8143 [doi]

Self-Calibrated Delay-Based LSB Extraction for Resolution Improvement in SAR ADCsAyca Akkaya, Firat Celik, Yusuf Leblebici. norchip 2019: 1-7 [doi]

A Hardware Inference Accelerator for Temporal Convolutional NetworksRashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey. norchip 2019: 1-7 [doi]

An All-Digital Duty-Cycle Corrector for Parallel High-Speed I/O LinksNico Angeli, Klaus Hofmann. norchip 2019: 1-6 [doi]

Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-PropagationMark G. Arnold, Ed Chester, John R. Cowles, Corey Johnson. norchip 2019: 1-6 [doi]

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL SlicingAhmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer 0001. norchip 2019: 1-7 [doi]

The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning ApplicationsAneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin. norchip 2019: 1-7 [doi]

Dual-Stage Phase UnwrappingBardia Barabadi, Matthew Gara, Ali Jooya, Amirali Baniasadi, Nikitas Dimopoulos. norchip 2019: 1-7 [doi]

IEEE 802.11ad SC-PHY Layer Simulator: Performance in Real-world 60 GHz Indoor ChannelsJiri Blumenstein, Jiri Milos, Ladislav Polak, Christoph F. Mecklenbräuker. norchip 2019: 1-4 [doi]

A Real-Time Fast Ethernet Transceiver achieving Sub-ns Time SynchronizationSimon Buhr, Martin Kreißig, Frank Ellinger. norchip 2019: 1-7 [doi]

HALib: Hardware Assertion Library for on-board verification of FPGA-based modules using HLSJulián Caba, F. Rincón, J. Barba, J. A. de la Torre, Julio Dondo, J. C. López. norchip 2019: 1-7 [doi]

A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural NetworksSteinar Thune Christensen, Snorre Aunet, Omer Qadir. norchip 2019: 1-6 [doi]

A Fault-Tolerant Time-Predictable ProcessorChristos Gkiokas, Martin Schoeberl. norchip 2019: 1-6 [doi]

Towards a Python-Based One Language Ecosystem for Embedded Systems AutomationZhao Han, Keerthikumara Devarajegowda, Michael Werner, Wolfgang Ecker. norchip 2019: 1-7 [doi]

A 500mV, 118nW, ∑Δ-Modulator ADC for Audio Detection in 28 nm FD-SOIMarkus Mogensen Henriksen, Dennis Øland Larsen, Pere Llimós Muntal, Ivan H. H. Jørgensen. norchip 2019: 1-6 [doi]

Optimizing Inductorless Static CML Frequency Dividers up to 23GHz Output Using 45nm CMOS PD-SOIMikko Hietanen, Janne Aikio, Alok Sethi, Rehman Akbar, Timo Rahkonen, Aarno Pärssinen. norchip 2019: 1-4 [doi]

Linearization of Active Transmitter Arrays in Presence of Antenna Crosstalk for 5G SystemsFeridoon Jalili, Martin H. Nielsen, Ming Shen, Ole K. Jensen, Jan H. Mikkelsen, Gert Frølund Pedersen. norchip 2019: 1-5 [doi]

A Time-Based Control Scheme for Power Factor Correction Boost ConverterChristopher H. K. Jensen, Rasmus B. Lind, Jens Christian Hertel, Ahmed M. Ammar, Arnold Knott, Michael A. E. Andersen. norchip 2019: 1-6 [doi]

MemOpt: Automated Memory Distribution for Multicore Microcontrollers with Hard Real-Time RequirementsPhilipp Jungklass, Mladen Berekovic. norchip 2019: 1-7 [doi]

Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH CodesE. Kavvousanos, Vassilis Paliouras. norchip 2019: 1-6 [doi]

Single Burst Depth-Resolving Raman Spectrometer Based on a SPAD Array with an On-Chip TDC to Analyse Heterogenous Liquid SamplesJere Kekkonen, Ilkka Nissinen. norchip 2019: 1-5 [doi]

Fast Fixed-point Bicubic Interpolation Algorithm on FPGAJanne Koljonen, Vladimir A. Bochko, Sami J. Lauronen, Jarmo T. Alander. norchip 2019: 1-7 [doi]

An Analogue Baseband Chain for a Magnetic Tunnel Junction Based RF Signal DetectorRui Ma, Simon Buhr, Zoltán Tibenszky, Martin Kreißig, Frank Ellinger. norchip 2019: 1-6 [doi]

Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital FiltersLavanya Maddisetti, J. V. R. Ravindra. norchip 2019: 1-6 [doi]

HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoCMohammad Amir Mansoori, Mario R. Casu. norchip 2019: 1-7 [doi]

T-LINC Architecture with Digital Combination and Mismatch Correction in the ReceiverEmilio J. Martínez-Pérez, Feridoon Jalili, Ming Shen, Jan H. Mikkelsen, Ole K. Jensen, Gert Frølund Pedersen. norchip 2019: 1-5 [doi]

A 36 nW trimless voltage reference with low sensitivity to PVT variationsCalvin Maxsen, Pere Llimós Muntal, Gunnar Gudnason, Ivan H. H. Jørgensen. norchip 2019: 1-5 [doi]

A 40-GHz Fully-Integrated CMOS-Based Biosensor Circuit with an On-Chip Vector Network Analyzer for Circulating Tumor Cells AnalysisTaiki Nakanishi, Shunya Murakami, Atsuki Kobayashi, Md. Zahidul Islam, Kiichi Niitsu. norchip 2019: 1-7 [doi]

End-to-End Approximation for Characterizing Energy Efficiency of IoT ApplicationsMohammadreza Nakhkash, Anil Kanduri, Amir M. Rahmani, Pasi Liljeberg. norchip 2019: 1-6 [doi]

Practical Stimulus Design for a Multi-Tone FitMarko Neitola. norchip 2019: 1-7 [doi]

Two-Stage Internal DAC Mismatch Mitigation for a Continuous-Time Delta-Sigma ADCMarko Neitola. norchip 2019: 1-7 [doi]

A New Interpretation to Groszkowski's EffectMostafa Jafari Nokandi, Sumit Pratap Singh, Aarno Pärssinen, Timo Rahkonen. norchip 2019: 1-4 [doi]

2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip (SoC), Helsinki, Finland, October 29-30, 2019Jari Nurmi, Peeter Ellervee, Kari Halonen, Juha Röning, editors, IEEE, 2019. [doi]

A Real-Time Gesture Recognition System with FPGA Accelerated ZynqNet ClassificationRicardo Núñez-Prieto, Pablo Correa Gómez, Liang Liu. norchip 2019: 1-6 [doi]

Instruction Extension of a RISC-V Processor Modeled with IP-XACTSaman Payvar, Esko Pekkarinen, Rafael Stahl, Daniel Mueller-Gritschneder, Timo D. Hämäläinen. norchip 2019: 1-5 [doi]

Semantic segmentation with inexpensive simulated dataJukka Peltomäki, Mengyang Chen, Heikki Huttunen. norchip 2019: 1-6 [doi]

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAMJohn Reuben, Dietmar Fey. norchip 2019: 1-6 [doi]

Ka-Band Stacked Power Amplifier on 22 nm CMOS FDSOI Technology Utilizing Back-Gate Bias for Linearity ImprovementJere Rusanen, Mikko Hietanen, Alok Sethi, Timo Rahkonen, Aarno Pärssinen, Janne P. Aikio. norchip 2019: 1-4 [doi]

On Applications of Configurable Approximation to Irregular VoltageToshinori Sato, Tomoaki Ukezono. norchip 2019: 1-6 [doi]

Designing at Millimeter-Wave: Lessons from a Triple Coil Variable TransformerAlok Sethi, Rehman Akbar, Janne P. Aikio, Rana A. Shaheen, Aarno Pärssinen, Timo Rahkonen. norchip 2019: 1-4 [doi]

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space ApplicationsAzam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg. norchip 2019: 1-6 [doi]

Layout Optimization Techniques for $r_{g}$ and, $f_{max}$ of Cascode Devices for mm Wave ApplicationsRana A. Shaheen, Timo Rahkonen, Rehman Akbar, Janne P. Aikio, Alok Sethi, Aarno Pärssinen. norchip 2019: 1-4 [doi]

Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCsArthur Silitonga, Zhou Jiang, Nadir Khan, Jürgen Becker. norchip 2019: 1-7 [doi]

Dynamic Resource Allocation for HEVC Encoding in FPGA-Accelerated SDN CloudPanu Sjövall, Arto Oinonen, Mikko Teuho, Jarno Vanne, Timo D. Hämäläinen. norchip 2019: 1-5 [doi]

1/f-Noise and Offset Cancellation for Rail-to-Rail Single-Slope ADCs in MEA ApplicationsLukas Straczek, Dominik J. Veit, Jürgen Oehm. norchip 2019: 1-5 [doi]

A 5 GHz CT $\Delta\sum$ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOSSiyu Tan, Lars Sundström, Mattias Palm, Sven Mattisson, Pietro Andreani. norchip 2019: 1-4 [doi]

Novel Clocking Scheme with Improved Voltage Gain for a Two-Phase Charge Pump TopologyJakob Kenn Toft, Ivan H. H. Jørgensen. norchip 2019: 1-7 [doi]

A 300mV-Supply Standard-Cell-Based OTA with Digital PWM Offset CalibrationPedro Toledo, Orazio Aiello, Paolo Stefano Crovetti. norchip 2019: 1-5 [doi]

Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded SystemsRuben Vazquez, Ann Gordon-Ross, Greg Stitt. norchip 2019: 1-7 [doi]

Sphere Decoder for Massive MIMO SystemsDimitris Vordonis, Vassilis Paliouras. norchip 2019: 1-6 [doi]

How Diversity Affects Deep-Learning Side-Channel AttacksHuanyu Wang, Martin Brisfors, Sebastian Forsmark, Elena Dubrova. norchip 2019: 1-7 [doi]

Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone AdderSomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. norchip 2019: 1-7 [doi]

Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI TechnologySomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. norchip 2019: 1-6 [doi]

An AFE for Catheter-Based IEGM sensing with Inverter-based SAR ADCYuchen Zhao, Haoming Chu, Bengt Källbäck, Yajie Qin, Zhuo Zou, Lirong Zheng 0001. norchip 2019: 1-5 [doi]

An Explicitly Parallel Architecture for Packet Processing in Software Defined NetworksHesam Zolfaghari, Davide Rossi, Jari Nurmi. norchip 2019: 1-7 [doi]

2018

Flying-Capacitor Bottom-Plate Sampling Scheme for Low-Power High-Resolution SAR ADCsDmitry Osipov 0001, Steffen Paul. norchip 2018: 1-4 [doi]

Design Considerations and Evaluation of a High-Speed SAR ADCVictor Aberg, Christian Fager, Lars Svensson. norchip 2018: 1-6 [doi]

Noise Considerations in Pulse-Shaping Based TIA Channel Designed for a Pulsed TOF Laser Radar ReceiverAram Baharmast, Juha Kostamovaara. norchip 2018: 1-6 [doi]

Insertion-Loss Optimization of Transformer-based Matching Networks for mm-Wave ApplicationsDavid Bierbuesse, Renato Negra. norchip 2018: 1-5 [doi]

A 15-50GHz Multiplexer Circuit in 130nm SiGe BiCMOS Technology for Ultra-Wide Frequency Ramps in FMCW RadarFrank Herzel, Arzu Ergintav, Johannes Borngräber, Dietmar Kissinger. norchip 2018: 1-4 [doi]

Characterization and Considerations for Upset in FPGAChristian Johansson, Torbjorn Manefjord. norchip 2018: 1-4 [doi]

Unleashing the full power of feed-forward opamps: a 200MHz, fully differential, conditionally stable, 36dB gain PGA, using a four-stage multi-path 2.5V amplifier with double feed-forward compensationVahur Kampus, Martin Trojer, Robert Teschner. norchip 2018: 1-5 [doi]

A Row-Column Accessed Dynamic Element Matching DAC Architecture for SAR ADCsMustafa Kilic, Selman Ergünay, Yusuf Leblebici. norchip 2018: 1-5 [doi]

Dynamically Reconfigurable Gearbox Switched-Capacitor DC-DC ConverterDennis Oland Larsen, Martin Vinter, Ivan H. H. Jørgensen. norchip 2018: 1-5 [doi]

Low-Power Regulator for Micro Energy Harvesting ApplicationsTapani Nevalainen, Esteban Ferro, Victor M. Brea, Paula López, Ari Paasio. norchip 2018: 1-5 [doi]

Time-gated CMOS SPAD and a Quantum Well Laser Diode with a CMOS Driver for Time-Resolved Diffuse Optics ImagingJan Nissinen, Ilkka Nissinen, S. Jahromi, T. Talala, Juha Kostamovaara. norchip 2018: 1-4 [doi]

A Configurable Hysteresis Comparator for Asynchronous Sigma-Delta ModulatorsOlaitan Olabode, Vishnu Unnikrishnan, Ilia Kempi, Andreas Hammer, Marko Kosunen, Jussi Ryynänen. norchip 2018: 1-4 [doi]

Analysis and Design of ESD Protection for Robust Low-Power Pierce Crystal Oscillator StartupKim B. Ostman, Erlend Strandvik, Phil Corbishley, Tor Oyvind Vedal, Mika Salmi. norchip 2018: 1-4 [doi]

Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power TransistorsJacob E. F. Overgaard, Jens Christian Hertel, Jens Pejtersen, Arnold Knott. norchip 2018: 1-6 [doi]

Building Lumped Models for Measured Passive mm-wave ComponentsEero Sankila, Veeti Kiuru, Janne Aikio, Timo Rahkonen. norchip 2018: 1-4 [doi]

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