Journal: IEEE Design & Test of Computers

Volume 14, Issue 3

0 -- 0. News
7 -- 8Luciano Lavagno, Nanette Collins. DAC 97 Panel: Next-Generation HDLs
8 -- 10. Conference Reports
11 -- 14Gadi Singer. The Future of Test and DFT
15 -- 16Tony Ambler, Magdy S. Abadir. Design and Test Economics-An Extra Dimension
17 -- 23José M. Miranda. A BIST and Boundary-Scan Economics Framework
24 -- 35James Debardelaben, Vijay K. Madisetti, Anthony J. Gadient. Incorporating Cost Modeling in Embedded-System Design
36 -- 40Craig T. Pynn. Analyzing Manufacturing Test Costs
41 -- 44Jon Turino. Test Economics in the 21st Century
45 -- 50Magdy S. Abadir, Rohit Kapur. Cost-Driven Ranking of Memory Elements for Partial Intrusion
51 -- 58Des Farren, Anthony P. Ambler. The Economics of System-Level Testing
59 -- 69Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson. IC Failure Analysis: Magic, Mystery, and Science
70 -- 75Donald Staab, Eugene R. Hnatek. Diagnosing IC Failures in a Fast Environment
76 -- 82David P. Vallett. IC Failure Analysis: The Importance of Test and Diagnostics
83 -- 89Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena. Automated Diagnosis in Testing and Failure Analysis
90 -- 97Keith Baker, Jos van Beers. Shmoo Plotting: The Black Art of IC Testing
98 -- 103Robert C. Aitken. Modeling the Unmodelable: Algorithmic Fault Diagnosis
104 -- 112Mario Zagar, Danko Basch. Microprocessor Architecture Design with ATLAS
113 -- 121. A D&T Roundtable: Built-In Self-Test for Designers
123 -- 125. Design Automation Technical Committee Newsletter
126 -- 127. Test Technology Tc Newsletter
128 -- 0Jerry M. Soden, Christopher L. Henderson. Still in the Stone Age?