Journal: IEEE Design & Test of Computers

Volume 14, Issue 4

1 -- 0. D&T to greet new EIC
4 -- 5Victor P. Nelson. Which tester is right for your MCM?
5 -- 6. Conference Reports
7 -- 13Burton J. Smith. Burton Smith s Multithreaded Success Strategy
14 -- 0Yervant Zorian, Rajesh K. Gupta. Design and Test of Core-Based Systems on Chips
15 -- 25Rajesh K. Gupta, Yervant Zorian. Introducing Core-Based System Design
26 -- 35Ann Marie Rincon, Cory Cherichetti, James A. Monzel, David R. Stauffer, Michael T. Trick. Core Design and System-on-a-Chip Integration
36 -- 41Frank S. Eory. A Core-Based System-to-Silicon Design Methodology
42 -- 51Vijay K. Madisetti, Lan Shen. Interface Design for Core-Based Systems
52 -- 59Nur A. Touba, Bahram Pouya. Using Partial Isolation Rings to Test Core-Based Designs
60 -- 68Mika Kuulusa, Jari Nurmi, Janne Takala, Pasi Ojala, Henrik Herranen. A Flexible DSP Core for Embedded Systems
69 -- 77Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto, Enrico Macii, Massimo Poncino. Testing Core-Based Systems: A Symbolic Methodology
78 -- 86Keith A. Jenkins. Detecting and Preventing Measurement Errors
87 -- 94Al Crouch, Jeff Freeman. Designing and Verifying Embedded Microprocessors
95 -- 102. A D&T Roundtable: What s Next for Microelectronics Education?
103 -- 107. IEEE Design & Test of Computers: 1997 Annual Index, Volume 14
108 -- 109. DDATC Newsletter
110 -- 111. Tttc Newsletter
112 -- 0Lee Whetsel. A silicon El Niño?

Volume 14, Issue 3

0 -- 0. News
7 -- 8Luciano Lavagno, Nanette Collins. DAC 97 Panel: Next-Generation HDLs
8 -- 10. Conference Reports
11 -- 14Gadi Singer. The Future of Test and DFT
15 -- 16Tony Ambler, Magdy S. Abadir. Design and Test Economics-An Extra Dimension
17 -- 23José M. Miranda. A BIST and Boundary-Scan Economics Framework
24 -- 35James Debardelaben, Vijay K. Madisetti, Anthony J. Gadient. Incorporating Cost Modeling in Embedded-System Design
36 -- 40Craig T. Pynn. Analyzing Manufacturing Test Costs
41 -- 44Jon Turino. Test Economics in the 21st Century
45 -- 50Magdy S. Abadir, Rohit Kapur. Cost-Driven Ranking of Memory Elements for Partial Intrusion
51 -- 58Des Farren, Anthony P. Ambler. The Economics of System-Level Testing
59 -- 69Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson. IC Failure Analysis: Magic, Mystery, and Science
70 -- 75Donald Staab, Eugene R. Hnatek. Diagnosing IC Failures in a Fast Environment
76 -- 82David P. Vallett. IC Failure Analysis: The Importance of Test and Diagnostics
83 -- 89Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena. Automated Diagnosis in Testing and Failure Analysis
90 -- 97Keith Baker, Jos van Beers. Shmoo Plotting: The Black Art of IC Testing
98 -- 103Robert C. Aitken. Modeling the Unmodelable: Algorithmic Fault Diagnosis
104 -- 112Mario Zagar, Danko Basch. Microprocessor Architecture Design with ATLAS
113 -- 121. A D&T Roundtable: Built-In Self-Test for Designers
123 -- 125. Design Automation Technical Committee Newsletter
126 -- 127. Test Technology Tc Newsletter
128 -- 0Jerry M. Soden, Christopher L. Henderson. Still in the Stone Age?

Volume 14, Issue 2

0 -- 0Ivo Bolsens, Marco Cecchini. IP-based business conflicts
2 -- 3. VHDL fault injection questioned
3 -- 0. News
5 -- 13. Adventures in the Mainframe Trade
14 -- 15Peter Marwedel, Carlos A. López-Barrio. Guest Editor s Introduction: Design, Design Automation, and Test in Europe
16 -- 25Clifford Liem, François Naçabal, Carlos A. Valderrama, Pierre G. Paulin, Ahmed Amine Jerraya. System-on-a-Chip Cosimulation and Compilation
26 -- 33Manoj Sachdev. Open Defects in CMOS RAM Address Decoders
34 -- 39Jean-Michel Karam, Bernard Courtois, Hicham Boutamine. CAD Tools for Bridging Microsystems and Foundries
40 -- 50Reinaldo A. Bergamaschi, Salil Raje. Observable Time Windows: Verifying High-Level Synthesis Results
51 -- 59Rolf Drechsler, Bernd Becker, Stefan Ruppertz. The K*BMD: A Verification Data Structure
60 -- 71Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras. Fault-Secure Parity Prediction Arithmetic Operators
72 -- 80Rajesh K. Gupta, Stan Y. Liao. Using a Programming Language for Digital System Design
96 -- 0Scott Davidson. Why projects are late

Volume 14, Issue 1

0 -- 0J. Wilson. CFI leads development of design data standard
0 -- 0. News
4 -- 5. Keeping in touch: Reader survey results; planned e-mail survey
8 -- 9Marc E. Levitt. Guest Editor s Introduction: Microprocessors Lead the Way in Complex Design
10 -- 17Marc E. Levitt. Designing UltraSparc for Testability
18 -- 24Lynn Youngs, Siva Paramanandam. Mapping and Repairing Embedded-Memory Defects
25 -- 33Dilip K. Bhavsar, John H. Edmondson. Alpha 21164 Testability Strategy
34 -- 41Jainendra Kumar. Prototyping the M68060 for Concurrent Verification
42 -- 49Margarida F. Jacome, Viktor S. Lapinskii. NREC: Risk Assessment and Planning of Complex Designs
50 -- 54Robert Wu, Jerry Gerner, Richard Wheelus, Kevin Lew. Testing Logic-Intensive Memory ICs on Memory Testers
55 -- 63Al Bailey, Tim Lada, Jim Preston. Collateral ASIC Test
64 -- 74Ghassan Al Hayek, Yves Le Traon, Chantal Robach. Impact of System Partitioning on Test Cost
75 -- 83. Hardware-Software Codesign
84 -- 87. Panel Summaries
88 -- 90. Conference Reports
92 -- 93. Design Automation Technical Committee Newsletter
94 -- 95. Test Technology Tc Newsletter
96 -- 0Scott Davidson. George learns test