0 | -- | 0 | . News |
7 | -- | 8 | Luciano Lavagno, Nanette Collins. DAC 97 Panel: Next-Generation HDLs |
8 | -- | 10 | . Conference Reports |
11 | -- | 14 | Gadi Singer. The Future of Test and DFT |
15 | -- | 16 | Tony Ambler, Magdy S. Abadir. Design and Test Economics-An Extra Dimension |
17 | -- | 23 | José M. Miranda. A BIST and Boundary-Scan Economics Framework |
24 | -- | 35 | James Debardelaben, Vijay K. Madisetti, Anthony J. Gadient. Incorporating Cost Modeling in Embedded-System Design |
36 | -- | 40 | Craig T. Pynn. Analyzing Manufacturing Test Costs |
41 | -- | 44 | Jon Turino. Test Economics in the 21st Century |
45 | -- | 50 | Magdy S. Abadir, Rohit Kapur. Cost-Driven Ranking of Memory Elements for Partial Intrusion |
51 | -- | 58 | Des Farren, Anthony P. Ambler. The Economics of System-Level Testing |
59 | -- | 69 | Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson. IC Failure Analysis: Magic, Mystery, and Science |
70 | -- | 75 | Donald Staab, Eugene R. Hnatek. Diagnosing IC Failures in a Fast Environment |
76 | -- | 82 | David P. Vallett. IC Failure Analysis: The Importance of Test and Diagnostics |
83 | -- | 89 | Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena. Automated Diagnosis in Testing and Failure Analysis |
90 | -- | 97 | Keith Baker, Jos van Beers. Shmoo Plotting: The Black Art of IC Testing |
98 | -- | 103 | Robert C. Aitken. Modeling the Unmodelable: Algorithmic Fault Diagnosis |
104 | -- | 112 | Mario Zagar, Danko Basch. Microprocessor Architecture Design with ATLAS |
113 | -- | 121 | . A D&T Roundtable: Built-In Self-Test for Designers |
123 | -- | 125 | . Design Automation Technical Committee Newsletter |
126 | -- | 127 | . Test Technology Tc Newsletter |
128 | -- | 0 | Jerry M. Soden, Christopher L. Henderson. Still in the Stone Age? |