| 10 | -- | 17 | Brian Leslie, Farid Matta. Wafer-level testing with a membrane probe |
| 18 | -- | 24 | Francois J. Henley. An ultra high speed test system |
| 26 | -- | 34 | Rob Dekker, Frans P. M. Beenker, Loek Thijssen. Realistic built-in self-test for static RAMs |
| 36 | -- | 44 | Clay S. Gloster Jr., Franc Brglez. Boundary scan with built-in self-test |
| 45 | -- | 55 | Eun Sei Park, M. Ray Mercer, Thomas W. Williams. A statistical model for delay-fault testing |
| 56 | -- | 66 | Laurence E. Bays, Chin-Fu Chen, Evelyn M. Fields, Renato N. Gadenz, W. Patrick Hays, Howard S. Moscovitz, Thomas G. Szymanski. Post-layout verification of the WE DSP32 digital signal processor |