External Links

    Journal: IEEE Design & Test of Computers

    Volume 6, Issue 6

    6 -- 17Patrick Groeneveld. Wire ordering for detailed routing
    18 -- 31Pierre G. Paulin, John P. Knight. Algorithms for high-level synthesis
    32 -- 48Larry Soulé, Anoop Gupta. Parallel distributed-time logic simulation

    Volume 6, Issue 5

    8 -- 19Sudipta Bhawmik, P. Palchaudhuri. DFT Expert: designing testable VLSI circuits
    20 -- 28Y. S. Kuo, S. Y. Hwang, H. F. Hu. A data structure for fast region searches
    29 -- 39Young-Uk Yu. VLSI design and CAD technology in Korea
    40 -- 49Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada. Logic simulation engines in Japan
    50 -- 57Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh 0001, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar. Ideas: a tool for VLSI CAD
    58 -- 77Sheldon B. Akers Jr., Balakrishnan Krishnamurthy. Test counting: a tool for VLSI testing

    Volume 6, Issue 4

    18 -- 30Kenneth P. Parker. The impact of boundary scan on board test
    32 -- 48Bulent I. Dervisoglu. Scan-path architecture for pseudorandom testing
    49 -- 60John A. Waicukauski, Eric Lindbloom. Failure diagnosis of structured VLSI

    Volume 6, Issue 3

    8 -- 34M. Dannie Durand. Parallel simulated annealing: accuracy vs. speed in placement
    36 -- 42William T. Lee. Engineering a device for electron-beam probing
    50 -- 51Shigehiro Funatsu, Masato Kawai, Akihiko Yamada. Scan design at NEC
    58 -- 65Nagesh Vasanthavada, Nick Kanopoulos. A built-in test module for fault isolation

    Volume 6, Issue 2

    8 -- 17Viktors Berstis. The V compiler: automating hardware design
    18 -- 34Francky Catthoor, Jos van Sas, Luc Inze, Hugo De Man. A testability strategy for multiprocessor architecture
    35 -- 44Albert E. Casavant, Manuel A. d'Abreu, Martin Dragomirecky, David A. Duff, Jeffrey R. Jasica, Michael J. Hartman, Ki-Soo Hwang, William D. Smith. A synthesis environment for designing DSP systems

    Volume 6, Issue 1

    10 -- 17Brian Leslie, Farid Matta. Wafer-level testing with a membrane probe
    18 -- 24Francois J. Henley. An ultra high speed test system
    26 -- 34Rob Dekker, Frans P. M. Beenker, Loek Thijssen. Realistic built-in self-test for static RAMs
    36 -- 44Clay S. Gloster Jr., Franc Brglez. Boundary scan with built-in self-test
    45 -- 55Eun Sei Park, M. Ray Mercer, Thomas W. Williams. A statistical model for delay-fault testing
    56 -- 66Laurence E. Bays, Chin-Fu Chen, Evelyn M. Fields, Renato N. Gadenz, W. Patrick Hays, Howard S. Moscovitz, Thomas G. Szymanski. Post-layout verification of the WE DSP32 digital signal processor
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