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    Journal: IEEE Design & Test of Computers

    Volume 4, Issue 6

    4 -- 19Lindsay Kleeman, Antonio Cantoni. Metastable Behavior in Digital Systems
    22 -- 29Kazuhiro Ueda, Hitoshi Kitazawa, Tohru Adachi, Ikuo Harada. Top-Down Layout for Hierarchical Custom Design
    30 -- 40Janusz Rajski, Vinod K. Agarwal. Testing and Applications of Inverter-Free PLAs
    41 -- 44Walid A. Najjar, Jean-Luc Jezouin, Jean-Luc Gaudiot. Parallel Discrete-Event Simulation

    Volume 4, Issue 5

    19 -- 27Frederica Darema, Gregory F. Pfister. Multipurpose Parallelism for VLSI Cad on the RP3
    28 -- 36Prathima Agrawal, William J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, Raffi Tutundjian. MARS: A Multiprocessor-Based Programmable Accelerator
    38 -- 45Thomas Ryan, Edwin Rogers. An Isma Lee Router Accelerator

    Volume 4, Issue 4

    18 -- 25John P. Hayes. An Introduction to Switch-Level Modeling
    26 -- 40Randal E. Bryant. A Survey of Switch-Level Algorithms
    42 -- 49Dick L. Liu, Edward J. McCluskey. Designing CMOS Circuits for Switch-Level Testability
    50 -- 54Paul H. Bardell. TTTC 10th Anniversary

    Volume 4, Issue 3

    21 -- 31David R. Ditzel, Alan D. Berenbaum. Using CAD Tools in the Design of CRISP
    32 -- 40Hu H. Chao, Shauchi Ong, Mon Yen (Mike) Tsai, Feng-Hsien W. Shih, Kelvin W. Lewis, Jeffrey Yuh-Fong Tang, Cynthia A. Trempel, Hwa Nien Yu, Peter E. McCormick, Clinton V. Davis Jr., Andrew L. Diamond, Thomas J. Medve, John C. L. Hou. Designing the Micro/370
    42 -- 50Patrick P. Gelsinger. Design And Test of the 80386
    52 -- 58Shoji Horiguchi, Hiroshi Yoshimura, Mitsuyoshi Nagatani, Kennosuke Fukami. The Design of Dedicated 32-Bit Processors

    Volume 4, Issue 2

    12 -- 20Randall Kramer. Testing Mixed-Signal Devices
    22 -- 30Mark R. Barber, Walter I. Satre. Timing Accuracy in Modern ATE
    32 -- 38John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, Vijay S. Iyengar. Transition Fault Simulation
    39 -- 45Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke. Aliasing Errors in Signature Analysis Registers
    46 -- 54Alexander Miczo, Dipti Mohapatra, Scott Perkins, Katie Kaufman, Ken Huang. The Effects of Modeling on Simulator Performance

    Volume 4, Issue 1

    12 -- 22Randy H. Katz, Rajiv Bhateja, Ellis E. Chang, David Gedye, Vony Trijanto. Design Version Management
    24 -- 31Sy-Yen Kuo, W. Kent Fuchs. Efficient Spare Allocation for Reconfigurable Arrays
    32 -- 41Hiroyuki Watanabe. Flute an Expert Floor Planner for Full-Custom VLSI Design
    42 -- 51Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita. Built-In Self-Testing RAM: A Practical Alternative
    52 -- 54Sudhakar M. Reddy, Ramaswami Dandapani. Scan Design Using Standard Flip-Flops
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