| 789 | -- | 790 | Hideo Fujiwara. Foreword |
| 791 | -- | 795 | Hiromi Hiraishi. Towards Verification of Bit-Slice Circuits-Time-Space Modal Model Checking Approach- |
| 796 | -- | 801 | Sérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea, Hiromi Hiraishi. Temporal Verification of Real-Time Systems |
| 802 | -- | 810 | Yoshiaki Kakuda, Hideki Yukitomo, Shinji Kusumoto, Tohru Kikuno. A New Conformance Testing Technique for Localization of Multiple Faults in Communication Protocols |
| 811 | -- | 816 | Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita. Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis |
| 817 | -- | 821 | Koji Yamazaki, Teruhiko Yamada. A Single Bridging Fault Location Technique for CMOS Combinational Circuits |
| 822 | -- | 829 | Xiangqiu Yu, Hiroshi Takahashi, Yuzo Takamatsu. A Study for Testability of Redundant Faults in Combinational Circuits Using Delay Effects |
| 830 | -- | 838 | Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita. Testing of ::::k::::-FR Circuits under Highly Observable Condition |
| 839 | -- | 844 | Junichi Hirase, Masanori Hamada. The Effect of CMOS VLSI IDDq Measurement on Defect Level |
| 845 | -- | 852 | Yukiya Miura, Sachio Naito. A Method of Current Testing for CMOS Digital and Mixed-Signal LSIs |
| 853 | -- | 860 | Shigeharu Teshima, Naoya Chujo, Ryuta Terashima. Very Fast Fault Simulation for Voltage Stuck-at Faults in Analog/Digital Mixed Circuit |
| 861 | -- | 867 | Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita. Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement |
| 868 | -- | 873 | Takeshi Koyama, Ryuji Ohmura. A Practical Test System with a Fuzzy Logic Controller |
| 874 | -- | 881 | Tokumi Yokohira, Toshimi Shimizu, Hiroyuki Michinishi, Yuji Sugiyama, Takuji Okamoto. The Number of Elements in Minimum Test Set for Locally Exhaustive Testing of Combinational Circuits with Five Outputs |
| 882 | -- | 888 | Kiyoshi Furuya, Seiji Seki, Edward J. McCluskey. Design of Autonomous TPG Circuits for Use in Two-Pattern Testing |
| 889 | -- | 894 | Kiyoshi Furuya, Susumu Yamazaki, Masayuki Sato. Stuck-Open Fault Detectabilities of Various TPG Circuits for Use in Two-Pattern Testing |
| 895 | -- | 900 | Martin Kutrib, Roland Vollmar. The Firing Squad Synchronization Problem in Defective Cellular Automata |
| 901 | -- | 908 | Kensei Tsuchida. The Complexity of Drawing Tree-Structured Diagrams |
| 909 | -- | 916 | Satoshi Naoi, Maki Yabuki, Atsuko Asakawa, Yoshinobu Hotta. Global Interpolation in the Segmentation of Handwritten Characters Overlapping a Border |
| 917 | -- | 922 | Yasushi Kanazawa, Kenichi Kanatani. Direct Reconstruction of Planar Surfaces by Stereo Vision |