Journal: IEICE Transactions

Volume 90-A, Issue 12

2649 -- 2650Yusuke Matsunaga. Special Section on VLSI Design and CAD Algorithms
2651 -- 2660Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata. Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
2661 -- 2668Masanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera. Timing Analysis Considering Spatial Power/Ground Level Variation
2669 -- 2681Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai. Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines
2682 -- 2690Hirokazu Muta, Hidetoshi Onodera. Manufacturability-Aware Design of Standard Cells
2691 -- 2694Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi. Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM
2695 -- 2702Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto. Area Comparison between 6T and 8T SRAM Cells in Dual-::::V::::::dd:: Scheme and DVS Scheme
2703 -- 2711Jin-Fu Li, Chao-Da Huang. An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
2712 -- 2717Masanori Hashimoto, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa. Transistor Sizing of LCD Driver Circuit for Technology Migration
2718 -- 2726Tsung-Yi Wu, Jr-Luen Tzeng. A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
2727 -- 2735Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu. Opposite-Phase Clock Tree for Peak Current Reduction
2736 -- 2742Bakhtiar Affendi Rosdi, Atsushi Takahashi. Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements
2743 -- 2751Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura. A Relocation Method for Circuit Modifications
2752 -- 2761Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler. Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs
2762 -- 2769Munehiro Matsuura, Tsutomu Sasao. BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades
2770 -- 2777Taeko Matsunaga, Yusuke Matsunaga. Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
2778 -- 2789Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara. Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints
2790 -- 2799Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya. Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times
2800 -- 2809Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto. Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
2810 -- 2817Kohei Hosokawa, Katsunori Tanaka, Yuichi Nakamura. Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
2818 -- 2825Chun-Lung Hsu, Mean-Hom Ho. High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
2826 -- 2834Kazunori Kobayashi, Ken ichi Furuya, Youichi Haneda, Akitoshi Kataoka. An Approach to Solve Local Minimum Problem in Sound Source and Microphone Localization
2835 -- 2845Akihide Horita, Kenji Nakayama, Akihiro Hirano. A Distortion-Free Learning Algorithm for Feedforward Multi-Channel Blind Source Separation
2846 -- 2852Koji Asami. An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters
2853 -- 2862Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii. Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
2863 -- 2876Sang-Moon Soak. Adaptive Link Adjustment Applied to the Fixed Charge Transportation Problem
2877 -- 2883Soon Lee, Seung-Mook Baek, Jung-Wook Park, Young-Hyun Moon. Kalman-Filter Based Estimation of Electric Load Composition with Non-ideal Transformer Modeling
2884 -- 2890Shieh-Shing Lin. A Parallel Algorithm for NMNF Problems with a Large Number of Capacity Constraints
2891 -- 2902Shinji Inoue, Shigeru Yamada. Discrete Program-Size Dependent Software Reliability Assessment: Modeling, Estimation, and Goodness-of-Fit Comparisons
2903 -- 2907Naoki Kanayama, Shigenori Uchiyama. The Vanstone-Zuccherato Schemes Revisited
2908 -- 2915Kazuhiko Minematsu, Toshiyasu Matsushima. Improved MACs from Differentially-Uniform Permutations
2916 -- 2929Tsungnan Lin, C. Lee Giles. Group-Linking Method: A Unified Benchmark for Machine Learning with Recurrent Neural Network
2930 -- 2938Shangce Gao, Zheng Tang, Hongwei Dai, Jianchen Zhang. An Improved Clonal Selection Algorithm and Its Application to Traveling Salesman Problems
2939 -- 2944Yijing Chu, Heping Ding, Xiaojun Qiu. Robust Source Separation with Simple One-Source-Active Detection
2945 -- 2948Moon Ho Lee, Subash Shree Pokhrel, Wen Ping Ma. A Class of Cocyclic Quasi Jacket Block Matrix
2949 -- 2951Teruya Minamoto, Mitsuaki Yoshihara, Satoshi Fujii. A Digital Image Watermarking Method Using Interval Arithmetic
2952 -- 2956Akira Tanaka, Masaaki Miyakoshi. Fast Parameter Selection Algorithm for Linear Parametric Filters
2957 -- 2961Koan-Yuh Chang, Tsung-Lin Cheng. Covariance Control for Bilinear Stochastic Systems via Sliding Mode Control Concept
2962 -- 2964Dae Hyun Yum, Pil Joong Lee. Security Analysis of Zhu-Bao s Verifiably Committed Signature
2965 -- 2970Ryo Nomura, Toshiyasu Matsushima, Shigeichi Hirasawa. A Note on the epsilon-Overflow Probability of Lossless Codes
2971 -- 2974Seungwoo Han, Suckchel Yang, Yoan Shin. An Effective SLM-PRSC Hybrid Scheme for OFDM PAPR Reduction
2975 -- 2978Huy G. Vu, Ha H. Nguyen, David E. Dodds. Performance Bound for Finite-Length LDPC Coded Modulation
2979 -- 2984Tze-Yun Sung, Hsi-Chin Hsin. A Hybrid Image Coder Based on SPIHT Algorithm with Embedded Block Coding
2985 -- 2988Kazuhiro Ogata, Kokichi Futatsugi. State Machines as Inductive Types