| 385 | -- | 0 | Tadayoshi Enomoto. Foreword |
| 386 | -- | 390 | How-Rern Lin, Wei-Hao Chiu, Tsung-Yi Wu. A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates |
| 391 | -- | 400 | Ching-Hwa Cheng, Chin-Hsien Wang. CK::::V::dd::::::: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits |
| 401 | -- | 408 | Tsung-Yi Wu, Liang-Ying Lu. Low-Leakage and Low-Power Implementation of High-Speed Logic Gates |
| 409 | -- | 416 | Tadayoshi Enomoto, Nobuaki Kobayashi. Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit |
| 417 | -- | 422 | Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Naoki Kasai. Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros |
| 423 | -- | 432 | Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto. A Dependable SRAM with 7T/14T Memory Cells |
| 433 | -- | 443 | Takatsugu Ono, Koji Inoue, Kazuaki Murakami, Kenji Yoshida. Reducing On-Chip DRAM Energy via Data Transfer Size Optimization |
| 444 | -- | 452 | Wenjian Yu, Rui Shi, Chung-Kuan Cheng. Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design |
| 453 | -- | 459 | Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto. A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test |
| 468 | -- | 474 | Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai. An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise |
| 475 | -- | 482 | Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata. Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations |
| 483 | -- | 491 | Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura. Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment |
| 492 | -- | 499 | Susumu Kobayashi, Naoshi Doi. An Efficient Decoupling Capacitance Budgeting Methodology by Using Power-Capacitance Ratio |
| 500 | -- | 507 | Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui. An Efficient Algorithm for RTL Power Macro-Modeling and Library Building |
| 508 | -- | 516 | Hengliang Zhu, Xuan Zeng, Xu Luo, Wei Cai. Generalized Stochastic Collocation Method for Variation-Aware Capacitance Extraction of Interconnects Considering Arbitrary Random Probability |
| 517 | -- | 521 | Gi-Ho Park, Jung-Wook Park, Hoi-Jin Lee, Gunok Jung, Sung-Bae Park, Shin-Dug Kim. A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache |
| 522 | -- | 531 | Panuwat Dan-Klang, Ekachai Leelarasmee. Transient Simulation of Voltage and Current Distributions within Transmission Lines |
| 532 | -- | 538 | Atsushi Kuramoto, Tomohiko Kanie, Masato Adachi, Masashi Kato, Yuichi Noro, Takashi Takeo. Improvements in a Ferrite Core Permeability Dispersion Measurement Based on a Microstrip Line Method |
| 539 | -- | 549 | Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama. Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture |
| 550 | -- | 557 | Sheng-Lyang Jang, Chih-Yeh Lin, Cheng-Chen Liu, Jhin-Fang Huang. Dual-Band CMOS Injection-Locked Frequency Divider with Variable Division Ratio |
| 558 | -- | 563 | Zunchao Li, Ruizhi Zhang, Feng Liang, Zhiyong Yang. Analytical and Numerical Study of the Impact of Halos on Surrounding-Gate MOSFETs |
| 564 | -- | 575 | Takao Kihara, Hae-Ju Park, Isao Takobe, Fumiaki Yamashita, Toshimasa Matsuoka, Kenji Taniguchi. A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier |
| 576 | -- | 586 | Panan Potipantong, Phaophak Sirisuk, Soontorn Oraintara, Apisak Worapishet. FPGA Implementation of Highly Modular Fast Universal Discrete Transforms |
| 587 | -- | 588 | Huy-Binh Le, Seung-Tak Ryu, Sang-Gug Lee. A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones |
| 589 | -- | 591 | Joonhee Lee, Sungjun Kim, Sehyung Jeon, Woojae Lee, SeongHwan Cho. A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS |