757 | -- | 758 | Ryuichi Fujimoto. Foreword |
759 | -- | 765 | Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano. Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress |
766 | -- | 773 | Takayuki Fujita. Energy Harvesters for Human-Monitoring Applications |
774 | -- | 782 | Takao Kihara, Tomohiro Sano, Masakazu Mizokami, Yoshikazu Furuta, Mitsuhiko Hokazono, Takaya Maruyama, Tetsuya Heima, Hisayasu Sato. A Multiband LTE SAW-Less CMOS Transmitter with Source-Follower-Driven Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns |
783 | -- | 789 | Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Ichiro Seto, Ryuichi Fujimoto, Yasuo Unekawa. TM SoC in 65 nm CMOS |
790 | -- | 795 | Takahiro Nakamura, Tomomitsu Kitamura, Nobuhiro Shiramizu, Toru Masuda. A Wide-Tuning-Range VCO with Small VCO-Gain Variation for Multi-Band W-CDMA RFIC |
796 | -- | 803 | Tong Wang, Toshiya Mitomo, Naoko Ono, Shigehito Saigusa, Osamu Watanabe. A 60 GHz Power Amplifier with 10 GHz 1-dB Bandwidth and 13.6% PAE in 65 nm CMOS |
804 | -- | 812 | Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa. A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer |
813 | -- | 819 | Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa. A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells |
820 | -- | 827 | Ryota Sekimoto, Akira Shikata, Kentaro Yoshioka, Tadahiro Kuroda, Hiroki Ishikuro. An Adaptive DAC Settling Waiting Time Optimized Ultra Low Voltage Asynchronous SAR ADC in 40 nm CMOS |
828 | -- | 837 | Sung-Wook Jun, Lianghua Miao, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito. Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers |
838 | -- | 849 | Hyunui Lee, Masaya Miyahara, Akira Matsuzawa. Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers |
850 | -- | 858 | Keisuke Kato, Fumitaka Abe, Kazuyuki Wakabayashi, Chuan Gao, Takafumi Yamada, Haruo Kobayashi, Osamu Kobayashi, Kiichi Niitsu. Two-Tone Signal Generation for ADC Testing |
859 | -- | 866 | Hao Zhang, Mengshu Huang, Yimeng Zhang, Tsutomu Yoshihara. Self-Cascode MOSFET with a Self-Biased Body Effect for Ultra-Low-Power Voltage Reference Generator |
867 | -- | 874 | Yasuhiro Sugimoto, Kazuma Sakatoh. Circuit Techniques to Enhance Linearity and Intrinsic Gain to Realize a 1.2 V, 200 MHz, +10.3 dBm IIP3 and 7th-Order LPF in a 65 nm CMOS |
875 | -- | 883 | Naoya Azuma, Makoto Nagata. Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components |
884 | -- | 893 | Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata. Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation |
894 | -- | 902 | Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa. A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation |
903 | -- | 911 | Fei Li, Masaya Miyahara, Akira Matsuzawa. A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs |
912 | -- | 919 | Yutaka Arayashiki, Takashi Kamizono, Yukio Ohkubo, Taisuke Matsumoto, Yoshiaki Amano, Yutaka Matsuoka. High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2: 1 Multiplexer and 1: 2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors |
920 | -- | 922 | Kiichi Niitsu, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi. A Feed-Forward Time Amplifier Using a Phase Detector and Variable Delay Lines |
923 | -- | 934 | Hae-Chang Jeong, Kyung Whan Yeom. A Design of X-Band 40 W Pulse-Driven GaN HEMT Power Amplifier |
935 | -- | 941 | Takashi Kawamoto, Masato Suzuki, Takayuki Noto. Wide Frequency-Range Spread-Spectrum Clock Generator with Digital Modulation Control |
942 | -- | 945 | Jhin-Fang Huang, Wen Cheng Lai, Kun-Jie Huang. A 5.6-GHz 1-V Low Power Balanced Colpitts VCO in 0.18-µm CMOS Process |