External Links

    Journal: Integration

    Volume 6, Issue 3

    243 -- 261Nils Hedenstierna, Kjell O. Jeppson. A corner-based hierarchical circuit extractor
    263 -- 290Fabrizio Lombardi. Reconfiguration of hexagonal arrays by diagonal deletion
    291 -- 308Asim J. Al-Khalili, Dhamin Al-Khalili, K. Ammar. An algorithm for polygon conversion to boxes for VLSI layouts
    309 -- 328C.-L. Tse, W. Kinsner. A graph-based heuristic channel router
    329 -- 344Kil Su Eo, Chong-Min Kyung. A hardware accelerator for two-dimensional image analysis
    345 -- 359Lars Kühnel, Hartmut Schmeck. A closer look at VLSI multiplication

    Volume 6, Issue 2

    127 -- 146Y. C. Hsu, William J. Kubitz. ALSO: A system for chip floorplan design
    147 -- 178Francky Catthoor, Hugo De Man, Joos Vandewalle. SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters
    179 -- 199Wentai Liu, Ralph K. Cavin III. Rasterization theory, architectures, and implementations for a class of two-dimensional problems
    201 -- 212Selim G. Akl, Henk Meijer. On the bit complexity of parallel computations
    213 -- 227Satnam Singh Dlay. A practical IC design system for VLSI technology

    Volume 6, Issue 1

    1 -- 0Lambert Spaanenburg. Editorial
    3 -- 33Peter Widmayer, Lin S. Woo, C. K. Wong. Maximizing pin alignment in semi-custom chip circuit layout
    35 -- 57James P. Cohoon, Dana S. Richards. Optimal two-terminal α-β wire routing
    59 -- 82Marius V. A. Hâncu, Kenneth C. Smith. Implementing probabilistic algorithms on VLSI architectures
    83 -- 99P. Chuavalee, Laxmi N. Bhuyan. VLSI layout of binary tree structures
    101 -- 110Toufic Ezzedine, Veronique Tempier, Georges Sagnes. A 16-bit specialized processor design
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