| 263 | -- | 277 | Hao Shen, Qinru Qiu. Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling |
| 278 | -- | 289 | Péter Horváth 0002, Gábor Hosszú. ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies |
| 290 | -- | 297 | A. Jasuja, R. K. Sharma. A Design Approach for Efficient Multipliers for Wearable Technology |
| 298 | -- | 307 | Pooja Joshi, Saurabh Khandelwal, Shyam Akashe. Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL |
| 308 | -- | 315 | Konstantina Roumelioti, Georgia Tsirimokou, Costas Psychalinos. Ultra-Low Voltage Analog Pre-Processing Stage for Realizing the Pan-Tompkins Algorithm |
| 316 | -- | 322 | K. P. Pradhan, S. K. Mohapatra, P. K. Sahu. Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation |
| 323 | -- | 332 | Leonid Mats, Marlin H. Mickle, Ziqun Zhou, Joshua R. Stachel, Kara Bocan, Nicholas G. Franconi, Michael R. Rothfuss, Lee Berger, Tim Butler, Chris Ubinger, Scott Lauer, Vyasa Sai, Ervin Sejdic. A Paradigm Shift in Passive Radio Frequency Identification Tag Development and Manufacturing Flexibility to Provide Active Tag Functionality |
| 333 | -- | 339 | Moumita Chakraborty, Krishnendu Guha, Debasri Saha, Partha Mitra, Amlan Chakrabarti. Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications |
| 340 | -- | 348 | João Casaleiro, Luís B. Oliveira, Igor M. Filanovsky. Amplitude and Quadrature Errors of Two-Integrator Oscillator |
| 349 | -- | 358 | Mohamad Al Kadi Jazairli, Denis Flandre. A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization |
| 359 | -- | 365 | Ankur Goel, R. K. Sharma, A. K. Gupta. Replica Tracked Post Silicon Trimming Enabled Negative Bit Line Voltage Based Write Assist Scheme in SRAM Design |
| 366 | -- | 372 | Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar. Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs |
| 373 | -- | 374 | Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan. Selected Articles from the IEEE ISED 2014 Conference |
| 375 | -- | 386 | Sudip Ghosh 0001, Arijit Biswas, Santi Prasad Maity, Hafizur Rahaman. Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications |
| 387 | -- | 400 | Naresh Vemishetty, Arpit Jain, Aashish Amber, Sidharth Maheshwari, Agathya Jagirdar, Amit Acharyya. A Robust Reliable and Low Complexity on Chip f-QRS Detection and Identification Architecture for Remote Personalized Health Care Applications |
| 401 | -- | 405 | Bijoy A. Jose, Abhishek Agrawal. Improving Energy Efficiency of Virtual Machines with Timer Tick Variations |
| 406 | -- | 412 | Rahul Shrestha, Roy P. Paily. VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder |
| 413 | -- | 425 | Priyankar Talukdar. Power-Aware Automated Pipelining of Combinational Circuits |
| 426 | -- | 435 | S. Kala, S. Nalesh, S. K. Nandy, Ranjani Narayan. Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture |
| 436 | -- | 443 | D. N. Jagadish, M. S. Bhat. Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter |
| 444 | -- | 454 | Chikku Abraham, Babita Roslind Jose, Jimson Mathew. A Multiple Input Variable Output Switched Capacitor DC-DC Converter for Harnessing Renewable Energy and Powering LEDs |