| 0 | -- | 0 | Mateo Valero, Jordi Cortadella, Antonio González. Chairmen s introduction |
| 1 | -- | 11 | Manuel Silva, José Manuel Colom. Petri Nets applied to the modelling and analysis of computer architecture problems |
| 13 | -- | 0 | Lotfi A. Zadeh. Fuzzy logic, neural networks and soft computing |
| 15 | -- | 0 | José A. B. Fortes. Matching algorithms and architectures |
| 19 | -- | 24 | Vincent Néri, Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble. Hardware features of the static communication network of a parallel architecture |
| 25 | -- | 32 | Janusz Sosnowski. Fault tolerant multiple-bus interconnection networks |
| 33 | -- | 41 | Cruz Izu, Ramón Beivide, Chris R. Jesshope, Agustin Arruabarrena. Experimental evaluation of Mad Postman bidimensional routing networks |
| 43 | -- | 44 | Klaus Waldschmidt. Processor architecture I |
| 45 | -- | 52 | Henk Corporaal. Evaluating transport triggered architectures for scalar applications |
| 53 | -- | 60 | Henk Corporaal, Paul van der Arend. Move32int, a sea of gates realization of a high performance transport triggered architecture |
| 61 | -- | 68 | Peter Pfahler, Christof Nagel, Franz-Josef Rammig, Uwe Kastens. Design of a VLIW architecture constructed from standard RISC chips: A case study of hardware/software codesign |
| 69 | -- | 0 | Werner Grass. Session A3: System specification I |
| 71 | -- | 78 | Stefano Antoniazzi, Alessandro Balboni, William Fornaciari. X-Nets: A visual formalism for system specification and analysis |
| 79 | -- | 86 | Chris Ho-Stuart, Hussein Zedan, Ming Fang. Automated support for the formal specification and design of real-time systems |
| 87 | -- | 95 | K. Brink, Ronald Huijsman, Jan van Katwijk. SEAL A simple language for prototyping action-event specifications |
| 97 | -- | 98 | Peter Milligan. Distributed memory management |
| 99 | -- | 107 | Dimitris Lioupis, Nikos Kanellopoulos, Michalis Stefanidakis. The memory hierarchy of the CHESS computer |
| 109 | -- | 118 | Vincent Habchi, Ulrich Finger, Ciaran O Donnell. Some practical considerations for the implementer of the SCI network |
| 119 | -- | 130 | Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang. Conflict-free access to streams in multiprocessor systems |
| 131 | -- | 0 | Jordi Cortadella. Session B2: Processor Architecture II |
| 133 | -- | 140 | Edil S. Tavares Fernandes, Fernando M. B. Barbosa, David M. Simpson. Evaluating the Cost of conditional branches on the performance of superscalar machines |
| 141 | -- | 147 | Michael Schäfers. Branch optimization of the TOOBSIE2 RISC-processor and classification |
| 149 | -- | 159 | J. S. Aude, E. P. Lopes Filho, M. F. Martins, S. B. Pinto. Arco: A cost-effective and flexible hardware maze router |
| 163 | -- | 170 | Constantinos V. Papadopoulos, Abul Habbas el Zahni. Protection and routing algorithms for network management : The case of transmission networks |
| 171 | -- | 178 | LuÃs Moura Silva, João Gabriel Silva. DIP : Distributed Diagnosis Protocol |
| 179 | -- | 186 | S. Allegra, M. Annunziata, F. Cesaroni, C. Lunadei. PLANNER 4: A simulator to design packet switching data network |
| 187 | -- | 188 | Péter Kacsuk. Parallel software engineering |
| 189 | -- | 196 | B. Moisan, Yves Duthen, René Caubet. Tools for object-oriented SPMD programming |
| 197 | -- | 204 | Manuel I. Capel, José M. Troya, A. Palma. Distributed active objects: A methodological proposal and tool for distributed programming with transputer systems |
| 205 | -- | 212 | Wouter Joosen, Stijn Bijnens, Pierre Verbaeten. A reusable load balancer for parallel search problems |
| 213 | -- | 220 | Jean Paul Calvez, Olivier Pasquier. Real-time behavior monitoring for multi-processor systems |
| 221 | -- | 0 | István Erényi. VLSI testing and testability |
| 223 | -- | 228 | Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano. Fault behavior and testability of asynchronous CMOS circuits |
| 229 | -- | 236 | Cristiana Bolchini, Franco Fummi. FSM fault models impact on test performances |
| 237 | -- | 243 | K. Ivinskis. Redundancy analysis and removal for VLSI ASIC s |
| 245 | -- | 252 | Chouki Aktouf, Chantal Robach, Guy Mazaré. Memory testing in a massively parallel machine |
| 253 | -- | 0 | Konrad Klöckner. Advances in object-oriented design |
| 255 | -- | 263 | Peter Loborg, Tore Risch, Martin Sköld, Anders Törne. Active object oriented databases in control applications |
| 265 | -- | 272 | Yoonsook Lee, Songchun Moon. Heterogeneous schema integration method for multidatabase system |
| 273 | -- | 280 | J. Ayre, Derrick Glass, John G. Hughes, I. R. McChesney. Toward automated support for object-oriented modelling |
| 281 | -- | 289 | Markku Oivo. Incremental resources estimation with real-time feedback from measurement |
| 291 | -- | 0 | Helmut Rzehak. Local area networks |
| 293 | -- | 299 | J. D. Sandoval, F. A. Herrera, A. Suárez, C. Sandoval. Concurrent ring: Design and evaluation of a new Token Ring LAN |
| 301 | -- | 308 | Theodore Antonakopoulos, S. Koutroubinas, J. Koutsonikos, Vassilios Makios. A distributed bandwidth allocation algorithm for Gbit/s LANs |
| 309 | -- | 315 | F. Videira, Augusto Casaca. An ISDN primary rate interface for ethernet access |
| 319 | -- | 326 | Rafael Asenjo, Manuel Ujaldon, Emilio L. Zapata. Parallel WZ factorization on mesh multiprocessors |
| 327 | -- | 334 | Massimo Maresca, Pierpaolo Baglietto, A. Giordano. Image component labeling on reconfigurable processor array |
| 335 | -- | 342 | Domingo Giménez, Vicente Hernández, Antonio M. Vidal. Computing the generalized eigenvalues of symmetric positive definite pencils on networks of transputers |
| 345 | -- | 350 | Béla Fehér. Efficient synthesis of distributed vector multipliers |
| 351 | -- | 357 | D. E. Metafas, Evaggelinos P. Mariatos, Spiridon Nikolaidis, Constantinos E. Goutis. Implementation of Given s Rotation processors for DSP real-time applications |
| 359 | -- | 365 | Haralambos C. Karathanasis. On computing the 2-D discrete cosine transform using rotations |
| 367 | -- | 0 | Andrew M. Tyrrell. Session D3: Data base systems |
| 369 | -- | 376 | Jae Cheol Kwak, Songchun Moon. Visual query language for object-oriented databases: OQD |
| 377 | -- | 384 | Sukhoon Kang, Songchun Moon. Global query management in heterogeneous distributed database systems |
| 385 | -- | 392 | José Ramón González de MendÃvil, Carlos F. Alastruey, José Ramón Garitagoitia. A distributed deadlock detection algorithm for the AND model |
| 393 | -- | 0 | András Jávor. Logic design |
| 395 | -- | 402 | Antonio Lioy, Massimo Poncino. A study of the resetability of synchronous sequential circuits |
| 403 | -- | 410 | A. J. W. M. ten Berg, C. Huijs, Th. Krol. Relational algebra as formalism for hardware design |
| 411 | -- | 418 | Colin C. Charlton, Paul H. Leng, Mark Rivers. An object-oriented model of design evolution |
| 419 | -- | 420 | Richard McConnell. Parallelizing compiler techniques |
| 421 | -- | 428 | Chu-Sing Yang, Chien-Chih Chang, Jenn-Ming Yang, Tsung-Chuan Huang, K. C. Huang. Exact and efficient advanced loop interchange |
| 429 | -- | 436 | FermÃn Sánchez, Jordi Cortadella. Resource-constrained pipelining based on loop transformations |
| 437 | -- | 444 | Zdzislaw Szczerbinski. Optimal data dependence chaining in parallel loops |
| 447 | -- | 454 | Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Giovanni Nateri, Mauro Olivieri. An asynchronous approach to the RISC design of a micro-controller |
| 455 | -- | 465 | J. Kottsieper, Klaus Waldschmidt. Application of the novel associative programmable array-structure multi-match-PLA in synthesis of decomposed finite state machines |
| 467 | -- | 474 | Olivier Caron, Vincent Cordonnier, Georges Grimonprez. OCEAN: A hardware and software tool for design of future smart cards |
| 477 | -- | 484 | Kwei-Jay Lin, Kevin B. Kenny. Implementing and checking timing constraints in real-time programs |
| 485 | -- | 490 | Celio Estevan Moron, Hussein Zedan. On guaranteeing hard real-time tasks |
| 491 | -- | 499 | Jinhwan Kim, Heonshik Shin. Priority-driven concurrency control based on data conflict state in distributed real-time databases |
| 503 | -- | 509 | Luigi Carro, César A. M. Marcon, A. A. Suzim. SHC-SLX: A levelized compiled, event driven interpreted VLSI simulator |
| 511 | -- | 518 | L. Gómez, A. Hernández, A. Nunez. Timing analysis for DCFL/SDCFL VLSI circuits |
| 519 | -- | 525 | Paul E. Dunne, Chris J. J. Gittings, Paul H. Leng. Sequential and parallel strategies for the demand-driven simulation of logic circuits |
| 527 | -- | 0 | Stephen Winter. Application-driven architectures |
| 529 | -- | 537 | Lars Bengtsson, Kenneth Nilsson, Bertil Svensson. A processor array module for distributed, massively parallel, embedded computing |
| 539 | -- | 543 | C. W. Yung, Edward K. N. Yung. Design of an extended transputer processor farm system |
| 545 | -- | 551 | Alessandra Costa, Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri. A parallel architecture for the Color Doppler flow technique in ultrasound imaging |
| 553 | -- | 560 | Luis Angel Barragan, Armando Roy. An empirical study of automatic restructuring of vision programs for simd machines |
| 563 | -- | 570 | Cristiana Bolchini, Massimo Bombana, Patrizia Cavalloro, Claudio Costi, Franco Fummi, Giuseppe Zaza. A design methodology for the correct specification of VLSI systems |
| 571 | -- | 580 | Johannes Helbig, Rainer Schlör, Werner Damm, Gert Döhmen, Peter Kelb. VHDL/S - integrating statecharts, timing diagrams, and VHDL |
| 581 | -- | 588 | Wolf-Dieter Tiedemann, Stefan Lenk, C. Grobe, Werner Grass. Introducing structure into behavioural descriptions obtained from timing diagram specifications |
| 589 | -- | 596 | Carlos Delgado Kloos, T. de Miguel Moro, T. Robles Valladares, G. Rabay Filho, Andrés MarÃn López. VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project |
| 597 | -- | 604 | SerafÃn Olcoz, José Manuel Colom. Analysis tools applied to VHDL |
| 607 | -- | 614 | K. Sacha. Real-time specification using Petri nets |
| 615 | -- | 623 | Achilles Kameas, Stergios Papadimitriou, Panayiotis E. Pintelas, Georgios Pavlides. IDFG: An interactive applications specification model with phenomenological properties |
| 625 | -- | 636 | Mariam Kamkar, Peter Fritzson, Nahid Shahmehri. Three approaches to interprocedural dynamic slicing |
| 637 | -- | 644 | Matthew J. Gallagher, V. Lakshmi Narasimhan. A software system for the generation of test data for Ada programs |
| 645 | -- | 0 | Kurt P. Judmann. Issues in distributed systems |
| 647 | -- | 654 | Hidenori Nakazato, Kwei-Jay Lin. Concurrency control algorithms for real-time systems |
| 655 | -- | 662 | V. Lakshmi Narasimhan, S. Price-White. Analysis and simulation of six bus arbitration protocols |
| 663 | -- | 668 | Kyösti Rautiola, Kari Pehkonen, Lauri Ståhle, Pekka Jokitalo. Design of TMS320C40 signal processors and programmable logic based prototyping environment of real-time machine vision architectures |
| 669 | -- | 678 | Achilles Kameas, Stergios Papadimitriou, Panayiotis E. Pintelas. Modeling and design of the multimedia subsystem of a distributed authoring environment |
| 679 | -- | 0 | Gerd Kock. Neural networks |
| 681 | -- | 688 | Thilo Reski. Mapping and parallel simulation of synchronous neural networks on multiprocessors |
| 689 | -- | 696 | Edoardo Franzi. Neural accelerator for parallelization of back-propagation algorithm |
| 697 | -- | 704 | Eran Tuv, Apostolos Nikolaos Refenes. Removal of catastrophic noise in hetero-associative training samples |
| 705 | -- | 706 | Lec Józwiak. Algorithms and tools for VLSI design |
| 707 | -- | 714 | Xin Yao. An empirical study of genetic operators in genetic algorithms |
| 715 | -- | 722 | Károly Tilly, Lászlo Surján, G. Román. Automatic test pattern generation can be solved as a constraint satisfaction problem |
| 723 | -- | 730 | Fausto Distante, P. Toccaceli. A behavioral level tool for design and verification of parallel architectures: PADS |
| 731 | -- | 0 | G. Ciccarella. Protocols and performance analysis |
| 733 | -- | 739 | Elena Pagani, Gian Paolo Rossi. Providing circuit service over a high speed deflection network |
| 741 | -- | 748 | Rumen Stainov. Dynamic protocol configuration for multimedia networks |
| 749 | -- | 755 | Aristotel Tentov, Aksenti L. Grnarov. Performance analysis of synchronous multibuffered packet-switching networks |
| 757 | -- | 0 | Francisco Tirado. RT-level synthesis |
| 759 | -- | 766 | S. Baranov, L. Bregman. Automata decomposition and synthesis with PLAM |
| 767 | -- | 774 | Christof Nagel. Synthesis for testability by synthesis controlling |
| 775 | -- | 782 | Rosa M. Badia, Jordi Cortadella. Glass: a graph-theoretical approach for global binding |
| 783 | -- | 0 | Karl-Erwin Grosspietsch. Session H1: Fault tolerance |
| 785 | -- | 792 | A. M. Tyrell, G. F. Carpenter. The design of time-critical conversations |
| 793 | -- | 800 | Sergio Arévalo, Jesús Carretero, J. L. Castellanos, F. Barco. A fault-tolerant server on MACH |
| 803 | -- | 809 | Bernd Klauer, Klaus Waldschmidt. Pen-based recognizing of handprinted characters |
| 811 | -- | 818 | Katerina Goseva-Popstojanova, Aksenti Grnarov. N version programming with majority voting decision: Dependability modeling and evaluation |
| 819 | -- | 0 | Harald Schummy. FDT Tools |
| 821 | -- | 825 | Katalin Tarnay, Gyula Csopaki, Maria Törö, M. D. Ta, Zs Boja-Harangozó, J. Miskolczi. Proconsul, a tool for computer-aided protocol engineering |
| 827 | -- | 832 | Maria Törö. Test strategy for indeterministic protocols |
| 835 | -- | 842 | L. P. M. Benders, M. P. J. Stevens. TL: A system specification system |
| 843 | -- | 850 | Gerd Kock, Nikola B. Serbedzija. Connectionist model description: A case study |