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    Journal: Journal of Systems Architecture

    Volume 46, Issue 9

    721 -- 747Andreas Steininger. Testing and built-in self-test - A survey
    749 -- 764S. J. Davis, C. J. Elston, P. A. Findlay. Register bypassing in an asynchronous superscalar processor
    765 -- 778Dongho Yoo, Inyoung Park, Seung Ryoul Maeng. Multistage ring network: An interconnection network for large scale shared memory multiprocessors
    779 -- 792Mohamed Ould-Khaoua, Lewis M. Mackenzie. On the design of hypermesh interconnection networks for multicomputers
    793 -- 807Anita Mittal, G. Manimaran, C. Siva Ram Murthy. Integrated dynamic scheduling of hard and QoS degradable real-time tasks in multiprocessor systems
    809 -- 833Yousef J. Al-Houmaily, Panos K. Chrysanthis. An atomic commit protocol for gigabit-networked distributed database systems

    Volume 46, Issue 8

    625 -- 626Andy M. Tyrrell, Stephen L. Smith. Heterogeneous distributed and parallel architectures: Hardware, software and design tools
    627 -- 639Howard Jay Siegel, Shoukat Ali. Techniques for mapping tasks to machines in heterogeneous computing systems
    641 -- 653Andrea Clematis, Gabriella Dodero, Vittoria Gianuzzi. Efficient use of parallel libraries on heterogeneous Networks of Workstations
    655 -- 673Jeong-Ki Kim, Jae-Woo Chang. Vertically-partitioned parallel signature file method
    675 -- 685Patricia González, José Carlos Cabaleiro, Tomás F. Pena. On parallel solvers for sparse triangular systems
    687 -- 698Kyungcheol Sohn, Songchun Moon. Achieving high degree of concurrency in multidatabase transaction scheduling: MTOS
    699 -- 719Inhwan Jung, Sonchung Moon. Transaction multicasting scheme for resilient routing control in parallel cluster database systems

    Volume 46, Issue 7

    551 -- 571Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis. Low power architectures for digital signal processing
    573 -- 585Kam-yiu Lam, Joseph Kee-Yin Ng. A conditional abortable priority ceiling protocol for scheduling mixed real-time tasks
    587 -- 600A. Castorino, G. Ciccarella. Algorithms for real-time scheduling of error-cumulative tasks based on the imprecise computation approach
    601 -- 605Rodrigo M. Santos, Jorge Santos, Javier Orozco, M. Zambón. Real-time multimedia standards in DQDB
    607 -- 617Nicolas Navet, Y. Q. Song, Françoise Simonot. Worst-case deadline failure probability in real-time applications distributed over controller area network
    619 -- 623Humayun Khalid. Validation of SPEC6:::TM::: CFP95 traces for accurate performance evaluation of computer systems

    Volume 46, Issue 6

    483 -- 511James Aweya. On the design of IP routers Part 1: Router architectures
    513 -- 517Abdullah Al-Shoshan, Mohammad A. Aloqeely. Systolic arrays architecture for computing the time-frequency spectrum
    519 -- 527Dajin Wang. The diagnosability of hypercubes with arbitrarily missing links
    529 -- 542Nabanita Das, Krishnendu Mukhopadhyaya, Jayasree Dattagupta. O(n) routing in rearrangeable networks
    543 -- 550Hai Jin, Kai Hwang. Stripped mirroring RAID architecture

    Volume 46, Issue 5

    411 -- 428D. Venkatesulu, Timothy A. Gonsalves, R. K. Hariram. On the performance of distributed objects
    429 -- 438Davide Anguita, Andrea Boni, Giancarlo Parodi. A case study of a distributed high-performance computing system for neurocomputing
    439 -- 454Jih-Kwon Peir, Windsor W. Hsu, Honesty C. Young, Shauchi Ong. Improving cache performance with Full-Map Block Directory
    455 -- 477D. De Almeida, P. Kellert. Markovian and analytical models for multiple bus multiprocessor systems with memory blockings

    Volume 46, Issue 4

    305 -- 325A. Burns, D. Prasad, Andrea Bondavalli, Felicita Di Giandomenico, Krithi Ramamritham, John A. Stankovic, Lorenzo Strigini. The meaning and role of value in scheduling flexible real-time systems
    327 -- 338Giuseppe Lipari, Giorgio C. Buttazzo. Schedulability analysis of periodic and aperiodic tasks with resource constraints
    339 -- 355Friedhelm Stappert, Peter Altenbernd. Complete worst-case execution time analysis of straight-line hard real-time programs
    357 -- 378José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings. Techniques to increase the schedulable utilization of cache-based preemptive real-time systems
    379 -- 395Anastasio Molano, Ángel Viña, Ragunathan Rajkumar. Operating system support for the management of hard real-time disk traffic
    397 -- 410S. H. Son. Issues and approaches to supporting timeliness and security in real-time database systems

    Volume 46, Issue 3

    209 -- 223Laurence Tianruo Yang, Zebo Peng. An improved register-transfer level functional partitioning approach for testability
    225 -- 242Giacomo Buonanno, Franco Fummi, Donatella Sciuto. An extended-UIO-based method for protocol conformance testing
    243 -- 258K. S. Loh, W. F. Wong. Multiple context multithreaded superscalar processor architecture
    259 -- 274Youngsik Kim, Tack-Don Han, Shin-Dug Kim. Impact of the memory interface structure in the memory-processor integrated architecture for computer vision
    275 -- 296László Szirmay-Kalos, Gábor Márton, Tibor Fóris, Tamás Horváth. Development of process visualization systems: An object-oriented approach
    297 -- 300Ujjwal Maulik, Sanghamitra Bandyopadhyay, Siddhartha Bhattacharyya. Fault tolerant permutation mapping in multistage interconnection network

    Volume 46, Issue 2

    105 -- 130M. Ajmone Marsan, F. Neri, C. Scarpati Cioffari, A. Vasco. GSPN models of bridged LAN configurations
    131 -- 144S. K. Kwon, Hyoung-Goo Jeon, Kyoung-Rok Cho. Optimum reserved resource allocation scheme for handoff in CDMA cellular system
    145 -- 162Antonio Puliafito, Orazio Tomarchio, Lorenzo Vita. MAP: Design and implementation of a mobile agents platform
    163 -- 179Shiao Li Tsao, Yueh-Min Huang, Jen-Wen Ding. Performance analysis of video storage server under initial delay bounds
    181 -- 199Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. A scheme for multiple on-chip signature checking for embedded SRAMS
    201 -- 205Novruz M. Allahverdi, Sirzad S. Kahramanli, Kayhan Erciyes. A fault tolerant routing algorithm based on cube algebra for hypercube systems

    Volume 46, Issue 15

    1365 -- 1382Jang-Soo Lee, Won-Kee Hong, Shin-Dug Kim. An on-chip cache compression technique to reduce decompression overhead and design complexity
    1383 -- 1402Nam-Kyu Lee, Sung-Bong Yang, Kyoung-Woo Lee. Efficient parity placement schemes for tolerating up to two disk failures in disk arrays
    1403 -- 1418JaeHo Jeon, Hyung-Sun Kim, GeonYoung Choi, HyunWook Park. KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing
    1419 -- 1433Giacomo Cabri, Letizia Leonardi, Franco Zambonelli. Agents for information retrieval: Issues of mobility and coordination
    1435 -- 1450Pao-Ann Hsiung. Embedded software verification in hardware-software codesign
    1451 -- 1467Jung Hoon Lee, Jang-Soo Lee, Shin-Dug Kim. A new cache architecture based on temporal and spatial locality
    1469 -- 1486Lieven Eeckhout, Henk Neefs, Koen De Bosschere. Early design stage exploration of fixed-length block structured architectures

    Volume 46, Issue 14

    1263 -- 1274Sri Parameswaran, Matthew F. Parkinson, Peter Bartlett. Profiling in the ASP codesign environment
    1275 -- 1291D. Vidya, Ranjani Parthasarathy, T. C. Bina, N. G. Swaroopa. Architecture for fractal image compression
    1293 -- 1308Won-Kee Hong, Shin-Dug Kim. A section cache system designed for VLIW architectures
    1309 -- 1319Andrew Bardsley, Doug A. Edwards. Synthesising an asynchronous DMA controller with Balsa
    1321 -- 1334Wolfgang Günther, Rolf Drechsler. ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs
    1335 -- 1348Vimal K. Khanna. A novel approach for implementing high-speed and long-distance networking protocols in a limited memory embedded kernel
    1349 -- 1364Muhammet Fikret Ercan, Yu-Fai Fung, M. Suleyman Demokan. Communication in a multi-layer MIMD system for computer vision

    Volume 46, Issue 13

    1159 -- 1173Ridha Djemal, Guy Mazaré, Rached Tourki. Rapid prototyping of an ATM programmable associative operator
    1175 -- 1184Gail-Joon Ahn. Role-based access control in DCOM
    1185 -- 1190Huiwei Guan, To-Yat Cheung. Efficient approaches for constructing a massively parallel processing system
    1191 -- 1204Inbum Jung, Jongwoong Hyun, Joonwon Lee. A scheduling policy for preserving cache locality in a multiprogrammed system
    1205 -- 1230Vladimir Vlassov, Rassul Ayani. Analytical modeling of multithreaded architectures
    1231 -- 1252Toshinori Sato. Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism
    1253 -- 1256Ioannis E. Pountourakis. Optimal bandwidth allocation and stability of high-speed networks for CSMA/CD protocols
    1257 -- 1261A. K. Bandyopadhyay, J. Bandyopadhyay. On the derivation of a correct deadlock free communication kernel for loop connected message passing architecture from its user s specification

    Volume 46, Issue 12

    1073 -- 1091H. Moharam, M. A. Abd El-Baky, S. M. M. Nassar. YOMNA - An efficient deadlock-free multicast wormhole algorithm in 2-D mesh multicomputers
    1093 -- 1102Ando Ki, Alan E. Knowles. Stride prefetching for the secondary data cache
    1103 -- 1114Samia Loucif, Mohamed Ould-Khaoua. On the relative performance merits of hypercube and hypermesh networks
    1115 -- 1135Wen-Fong Wang, Wen-Shyang Hwang, Jun-Yao Wang. Design of a large-scale Gbit/s MAN using a cyclic reservation-based MAC protocol
    1137 -- 1158Gianpiero Cabodi, Paolo Camurati, Stefano Quer. Symbolic forward/backward traversals of large finite state machines

    Volume 46, Issue 11

    955 -- 972Pasi Kolinummi, Timo Hämäläinen, Jukka Saarinen. Chained backplane communication architecture for scalable multiprocessor systems
    973 -- 990Stefanos Kaxiras. Distributed vector architectures
    991 -- 1004Rômulo Silva de Oliveira, Joni da Silva Fraga. Fixed priority scheduling of tasks with arbitrary precedence constraints in distributed hard real-time systems
    1005 -- 1012Hyojeong Song, Boseob Kwon, IkHyeon Jang, Hyunsoo Yoon. An output queueing analysis of multipath ATM switches
    1013 -- 1017Humayun Khalid. Performance evaluation of system architectures with validated input data
    1019 -- 1032Manuel P. Malumbres, José Duato. An efficient implementation of tree-based multicast routing for distributed shared-memory multiprocessors
    1033 -- 1046Heiko Oehring, Ulrich Sigmund, Theo Ungerer. Performance of simultaneous multithreaded multimedia-enhanced processors for MPEG-2 video decompression
    1047 -- 1071Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu. Efficient module selections for finding highly acceptable designs based on inclusion scheduling

    Volume 46, Issue 10

    835 -- 849Jacques Chassin de Kergommeaux, Alain Fagot. Execution replay of parallel procedural programs
    851 -- 871Mayez A. Al-Mouhamed, Adel Al-Massarani. Scheduling optimization through iterative refinement
    873 -- 888José L. Sánchez, José M. García. Dynamic reconfiguration of node location in wormhole networks
    889 -- 902Sukhoon Kang, Songchun Moon. Read-down conflict-preserving serializability as a correctness criterion for multilevel-secure optimistic concurrency control: CSR/RD
    903 -- 918Yunseok Rhee, Joonwon Lee. Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
    919 -- 930Tzung-Shi Chen, Chih-Yung Chang, Jang-Ping Sheu. Efficient path-based multicast in wormhole-routed mesh networks
    931 -- 949Francisco J. Suárez, Daniel F. García, Javier García. Measurement based analysis of temporal behaviour as support for scheduling problems in parallel and distributed real-time systems
    951 -- 954Gopal Racherla, Sridhar Radhakrishnan, L. S. DeBrunner. Parameterization of efficient dynamic reconfigurable trees

    Volume 46, Issue 1

    1 -- 21Paul J. M. Havinga, Gerard J. M. Smit. Design techniques for low-power systems
    23 -- 37Abdullah I. AlMojel, Tarek A. El-Ghazawi, Thomas L. Sterling. Characterizing and representing workloads for parallel computer architectures
    39 -- 47Andreas A. Veglis, Andreas S. Pombortsis, Efstathios Papaefstathiou. Performance evaluation of a bus-based multistage multiprocessor architecture
    49 -- 77Charlie McElhone, Alan Burns. Scheduling optional computations for adaptive real-time systems
    79 -- 95Alexander Romanovsky. Extending conventional languages by distributed/concurrent exception resolution
    97 -- 101S. Bhattacharya, M. Nasipuri. Traffic analysis in a double grain Dataflow array processor
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