Journal: Journal of Systems Architecture

Volume 53, Issue 9

551 -- 567Myungsu Choi, Zachary D. Patitz, Byoungjae Jin, Feng Tao, Nohpill Park, Minsu Choi. Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony
568 -- 576Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena. Low power data processing system with self-reconfigurable architecture
577 -- 586M. Akkal, Pepe Siy. A new Mixed Radix Conversion algorithm MRC-II
587 -- 601Ehsan Atoofian, Amirali Baniasadi. Speculative trivialization point advancing in high-performance processors
602 -- 618Rafal Kapela, Andrzej Rybarczyk. Real-time shape description system based on MPEG-7 descriptors
619 -- 628Dajin Wang. A heuristic fault-tolerant routing algorithm in mesh using rectilinear-monotone polygonal fault blocks
629 -- 643Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez. Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
644 -- 658Jeong-Uk Kang, Jinsoo Kim, Chanik Park, Hyoungjun Park, Joonwon Lee. A multi-channel architecture for high-performance NAND flash-based storage system
659 -- 676Andrea Santoro, Francesco Quaglia. Multiprogrammed non-blocking checkpoints in support of optimistic simulation on myrinet clusters

Volume 53, Issue 8

465 -- 0Jarmo Takala, Timo D. Hämäläinen, Andy D. Pimentel, Stamatis Vassiliadis. Editorial
466 -- 476Holger Blume, Thorsten von Sydow, Daniel Becker, Tobias G. Noll. Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
477 -- 488Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen. Benchmarking mesh and hierarchical bus networks in system-on-chip context
489 -- 500Frederik Vandeputte, Lieven Eeckhout, Koen De Bosschere. Exploiting program phase behavior for energy reduction on multi-configuration processors
501 -- 510Stefan Farfeleder, Andreas Krall, R. Nigel Horspool. Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
511 -- 523John McAllister, Roger Woods, Scott Fischaber, E. Malins. Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms
524 -- 538Chunhui Zhang, Yun Long, Fadi J. Kurdahi. A scalable embedded JPEG 2000 architecture
539 -- 549Marijn Temmerman, Edgar G. Daylight, Francky Catthoor, Serge Demeyer, Tom Dhaene. Optimizing data structures at the modeling level in embedded multimedia

Volume 53, Issue 7

339 -- 354Madhura Purnaprajna, Marek Reformat, Witold Pedrycz. Genetic algorithms for hardware-software partitioning and optimal resource allocation
355 -- 368Alejandro Martínez, Raúl Martínez, Francisco José Alfaro, José L. Sánchez. A low-cost strategy to provide full QoS support in Advanced Switching networks
369 -- 378J. Jyotheswar, Sudipta Mahapatra. Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression
379 -- 385Il-Gu Lee, Sok-Kyu Lee. Efficient automatic gain control algorithm and architecture for wireless LAN receivers
386 -- 402Bernd Scheuermann, Stefan Janson, Martin Middendorf. Hardware-oriented ant colony optimization
403 -- 416Jochen Hollmann, Anders Ardö, Per Stenström. Effectiveness of caching in a distributed digital library system
417 -- 436Stylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement
437 -- 452Jung-Shian Li, Chuan-Gang Liu, Cheng-Yu Huang. Achieving multipoint-to-multipoint fairness with RCNWA
453 -- 464Mozammel H. A. Khan, Marek A. Perkowski. Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Volume 53, Issue 5-6

251 -- 252Klaus Waldschmidt, Jan Haase, Werner Grass, Bernhard Sick. Editorial
253 -- 262Nabil Hasasneh, Ian Bell, Chris R. Jesshope. Asynchronous arbiter for micro-threaded chip multiprocessors
263 -- 271Xiaoyong Chen, Douglas L. Maskell. Supporting multiple-input, multiple-output custom functions in configurable processors
272 -- 284Woo-Chan Park, Cheong-Ghil Kim, Duk-Ki Yoon, Kil-Whan Lee, Il-San Kim, Tack-Don Han. A consistency-free memory architecture for sort-last parallel rendering processors
285 -- 299Jörg-Christian Niemann, Christoph Puttmann, Mario Porrmann, Ulrich Rückert. Resource efficiency of the GigaNetIC chip multiprocessor architecture
300 -- 309Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich. Efficient control generation for mapping nested loop programs onto processor arrays
310 -- 320Sunil Kim, Jun-Yong Lee. A system architecture for high-speed deep packet inspection in signature-based network intrusion prevention
321 -- 327Ralf Salomon, Frank Sill. High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
328 -- 337Sébastien Lafond, Johan Lilius. Energy consumption analysis for two embedded Java virtual machines

Volume 53, Issue 4

151 -- 169Tiberiu Seceleanu. The SegBus platform - architecture and communication mechanisms
170 -- 183Enric Morancho, José María Llabería, Àngel Olivé. A comparison of two policies for issuing instructions speculatively
184 -- 209Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi. Efficient FPGA hardware development: A multi-language approach
210 -- 226Ch. Rambabu, I. Chakrabarti. An efficient immersion-based watershed transform method and its prototype architecture
227 -- 232Ming-Chien Yang, Jimmy J. M. Tan, Lih-Hsing Hsu. Highly fault-tolerant cycle embeddings of hypercubes
233 -- 250F. J. Espino, Montserrat Bóo, Margarita Amor, Javier D. Bruguera. Hardware support for adaptive tessellation of Bézier surfaces based on local tests

Volume 53, Issue 2-3

69 -- 71Nadia Nedjah, Luiza de Macedo Mourelle. Embedded cryptographic hardware
72 -- 84Guerric Meurice de Dormale, Jean-Jacques Quisquater. High-speed hardware implementations of Elliptic Curve Cryptography: A survey
85 -- 98Robert Ronan, Colm O Eigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins. Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
99 -- 108Nadia Nedjah, Luiza de Macedo Mourelle. Fast hardware for modular exponentiation with efficient exponent pre-processing
109 -- 116Christophe Nègre. Efficient parallel multiplier in shifted polynomial basis
117 -- 126F. Bernard. Scalable hardware implementing high-radix Montgomery multiplication algorithm
127 -- 138Ryan Glabb, Laurent Imbert, Graham A. Jullien, Arnaud Tisserand, Nicolas Veyrat-Charvillon. Multi-mode operator for SHA-2 hash functions
139 -- 149Konrad J. Kulikowski, Mark G. Karpovsky, Alexander Taubin. Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard

Volume 53, Issue 12

889 -- 901Tae-Sun Chung, Hyung-Seok Park. STAFF: A flash driver algorithm minimizing block erasures
902 -- 912Huaxi Gu, Jie Zhang, Kun Wang, Zengji Liu, Guochang Kang. Enhanced fault tolerant routing algorithms using a concept of balanced ring
913 -- 926John A. Chandy. Dual actuator logging disk architecture and modeling
927 -- 936Wentong Li, Mehran Rezaei, Krishna M. Kavi, Afrin Naz, Philip H. Sweany. Feasibility of decoupling memory management from the execution pipeline
937 -- 950Ying-Dar Lin, Kuo-Kun Tseng, Tsern-Huei Lee, Yi-Neng Lin, Chen-Chou Hung, Yuan-Cheng Lai. A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection

Volume 53, Issue 11

795 -- 815Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen. Automated memory-aware application distribution for Multi-processor System-on-Chips
816 -- 832Li Chunlin, Li Layuan. Optimization decomposition approach for layered QoS scheduling in grid computing
833 -- 845Kuei-Chung Chang, Tien-Fu Chen. Efficient segment-based video transcoding proxy for mobile multimedia services
846 -- 860Ioannis Voyiatzis. Accumulator-based pseudo-exhaustive two-pattern generation
861 -- 876Yang Qu, Juha-Pekka Soininen, Jari Nurmi. Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
877 -- 887Wenfa Zhan, Huaguo Liang, Feng Shi, Zhengfeng Huang. Test data compression scheme based on variable-to-fixed-plus-variable-length coding

Volume 53, Issue 10

677 -- 678Timo D. Hämäläinen, Stephan Wong, John Glossner, Stamatis Vassiliadis. Editorial
679 -- 688Jari Heikkinen, Jarmo Takala. Effects of program compression
689 -- 702Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll. Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures
703 -- 718Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf. Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications
719 -- 732Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa. Exploration of distributed shared memory architectures for NoC-based multiprocessors
733 -- 750Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti. Efficient design space exploration for application specific systems-on-a-chip
751 -- 763Thilo Streichert, Michael Glaß, Christian Haubelt, Jürgen Teich. Design space exploration of reliable networked embedded systems
764 -- 776Hartwig Jeschke. Chip size estimation for SOC design space exploration
777 -- 793Stamatis Vassiliadis, Ioannis Sourdis. FLUX interconnection networks on demand

Volume 53, Issue 1

1 -- 20Lian Li 0002, Jingling Xue. Trace-based leakage energy optimisations at link time
21 -- 38Chen-Liang Fang, Deron Liang, Fengyi Lin, Chien-Cheng Lin. Fault tolerant Web Services
39 -- 52Dongmahn Seo, Joahyoung Lee, Yoon Kim, Changyeol Choi, Manbae Kim, Inbum Jung. Resource consumption-aware QoS in cluster-based VOD servers
53 -- 67Venkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj. An efficient variable partitioning approach for functional decomposition of circuits