| 741 | -- | 742 | José Silva Matos, Francesco Leporati. MICPRO DSD 2013 Special Issue |
| 743 | -- | 753 | Vincent Berg, Jean-Baptiste Doré, Dominique Noguet. A flexible radio transceiver for TVWS based on FBMC |
| 754 | -- | 765 | Jirí Balcárek, Petr Fiser, Jan Schmidt. On don't cares in test compression |
| 766 | -- | 775 | Yarkin Doröz, Erdinç Öztürk, Berk Sunar. A million-bit multiplier architecture for fully homomorphic encryption |
| 776 | -- | 787 | Daniele Bortolotti, Andrea Bartolini, Luca Benini. An ultra-low power resilient multi-core architecture with static and dynamic tolerance to ambient temperature-induced variability |
| 788 | -- | 802 | Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul. Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric |
| 803 | -- | 813 | Mehmet Ali Arslan, Krzysztof Kuchcinski. Instruction selection and scheduling for DSP kernels |
| 814 | -- | 825 | Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny. Designing single-cycle long links in hierarchical NoCs |
| 826 | -- | 842 | Guangda Zhang, Wei Song 0002, Jim D. Garside, Javier Navaridas, Zhiying Wang. Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes |
| 843 | -- | 844 | Peter M. Athanas, René Cumplido, Claudia Feregrino Uribe, Eduardo de la Torre. Introduction to Special issue on FPGA Devices and Applications |
| 845 | -- | 859 | Daniel Kliem, Sven-Ole Voigt. Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning |
| 860 | -- | 872 | Robin Bonamy, Sebastien Bilavarn, Daniel Chillet, Olivier Sentieys. Power consumption models for the use of dynamic and partial reconfiguration |
| 873 | -- | 888 | Shweta Jain-Mendon, Ron Sass. A hardware-software co-design approach for implementing sparse matrix vector multiplication on FPGAs |
| 889 | -- | 898 | Tannous Frangieh, Peter M. Athanas. A design assembly framework for FPGA back-end acceleration |
| 899 | -- | 910 | Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo. Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic |
| 911 | -- | 919 | Andreas Agne, Hendrik Hangmann, Markus Happe, Marco Platzner, Christian Plessl. Seven recipes for setting your FPGA on fire - A cookbook on heat generators |
| 920 | -- | 0 | Francesco Leporati, Lech Józwiak. Preface |
| 921 | -- | 932 | Salvador Trujillo, Alfons Crespo, Alejandro Alonso, Jon Pérez. MultiPARTES: Multi-core partitioning and virtualization for easing the certification of mixed-criticality systems |
| 933 | -- | 946 | Ivan Kastelan, Jorge R. Lopez Benito, Enara Artetxe Gonzalez, Jan Piwinski, Moshe Barak, Miodrag Temerinac. E2LP: A unified embedded engineering learning platform |
| 947 | -- | 959 | Erkan Diken, Roel Jordans, Rosilde Corvino, Lech Józwiak, Henk Corporaal, Felipe Augusto Chies. Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths |
| 960 | -- | 975 | Héctor Posadas, Alejandro Nicolás, Pablo Peñil, Eugenio Villar, Florian Broekaert, Michel Bourdellès, Albert Cohen, Mihai T. Lazarescu, Luciano Lavagno, Andrei Terechko, Miguel Glassee, Manuel Prieto. Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project |
| 976 | -- | 990 | Roberto Giorgi, Rosa M. Badia, François Bodin, Albert Cohen, Paraskevas Evripidou, Paolo Faraboschi, Bernhard Fechner, Guang R. Gao, Arne Garbade, Rahulkumar Gayatri, Sylvain Girbal, Daniel Goodman, Behram Khan, Souad Koliai, Joshua Landwehr, Nhat Minh Lê, Feng Li, Mikel Luján, Avi Mendelson, Laurent Morin, Nacho Navarro, Tomasz Patejko, Antoniu Pop, Pedro Trancoso, Theo Ungerer, Ian Watson, Sebastian Weis, Stéphane Zuckerman, Mateo Valero. TERAFLUX: Harnessing dataflow in next generation teradevices |
| 991 | -- | 999 | Hoda Naghibi Jouybari, Karim Mohammadi. A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips |
| 1000 | -- | 1011 | Mostafa Elhoushi, M. Watheq El-Kharashi, Hatem Elrefaei. Model of a hybrid processor executing C++ with additional quantum functions |
| 1012 | -- | 1024 | Chenglong Xiao, Emmanuel Casseau, Shanshan Wang, Wanjun Liu. Automatic custom instruction identification for application-specific instruction set processors |
| 1025 | -- | 1036 | Fenglong Song, Shibin Tang, Wenming Li, Futao Miao, Hao Zhang, Dongrui Fan, Zhiyong Liu. CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network |
| 1037 | -- | 1045 | Eman Kamel Gawish, M. Watheq El-Kharashi, M. F. Abu-Elyazeed. Variability-tolerant routing algorithms for Networks-on-Chip |
| 1046 | -- | 1062 | Moein Kianpour, Reza Sabbaghi-Nadooshan. A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata |
| 1063 | -- | 1071 | Vikas Kumar, Kailash Chandra Ray, Preetam Kumar. CORDIC-based VLSI architecture for real time implementation of flat top window |
| 1072 | -- | 1081 | Mojtaba Valinataj. A novel self-checking carry lookahead adder with multiple error detection/correction |